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High-speed low-distortion track-and-hold circuit

IP.com Disclosure Number: IPCOM000028217D
Publication Date: 2004-May-04
Document File: 2 page(s) / 24K

Publishing Venue

The IP.com Prior Art Database

Abstract

ID399968

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High-speed low-distortion track-and-hold circuit

Abstract

Today’s RF chains need high-speed circuits. In order to relax constraints of the whole circuit, it is preferable to use sample-and-hold (or track-and-hold) in front of the circuit. This interface must deals with frequency  up to several hundreds of megahertz, distortion less than –90dB for 2Vp-p input signal (example of analog-to-digital converter specification). Two kinds of track-and-hold are mainly used up to now (shown in figure 1 and 2) to reach high input frequency sampling. Track-and-hold in figure 2 definitely doesn’t reach the required distortion.

The present invention uses an emitter follower and introduces a novel technique to switch it on and off in order to achieve high-speed and low-distortion.

Description

Figure 1 shows a basic track-and-hold using a switch S0 and a capacitor Chold. The speed and distortion limit is given by the switch characteristics.

Figure 2 represents a track-and-hold based on an emitter follower Qswitch. In track mode, when Clock is high and Clockn is low, the current Ibias is flowing through Qswitch. In hold mode, when Clock is low and Clockn is high, Ibias flows through the buffer. This buffer is designed to give an output voltage lower than the voltage on Chold assuring that Qswitch is turned off. The frequency and distortion limitations of this kind of track-and-hold are given by the buffer.

The present invention is illustrated in figure 3. The emitter follower is switch...