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Current limit circuit

IP.com Disclosure Number: IPCOM000028251D
Publication Date: 2004-May-06
Document File: 2 page(s) / 59K

Publishing Venue

The IP.com Prior Art Database

Abstract

ID402350

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Current Limit Circuit

The circuit was developed as a result of the following requirements:

Current limit that was stable and reasonably precise.

Current limit would establish itself in a short time (<10us).

Integrated, precision, current measure function.

No reduction in device Rdson when operating well away from current limit.

The circuit uses a simple open loop function to provide the current limit utilising the forward transfer characteristic of the output mosfet, driven from a reference cell that is operating under controlled conditions.

When the device is operating at current levels significantly away from the current limit the circuit will flip into a low Rdson/high gate drive state.

M1, M2 and M3 are all cellular components of an integrated powermos structure (with well-matched cells by virtue of being on the same chip). M3 consists of the main body of powermos cells. M2 is a normally configured sense cell structure with its gate terminal connected to the gate terminal of M3.

M1 is a similar sense cell structure to M2 except its gate is isolated from the main gate structure of the powermos. OA and M4 function as a virtual earth current amplifier to impress a copy of the current flowing in M2 onto R (On the +ve input of the OTA). The OTA (operational transconductance amplifier) has a limited output such that the device can sink a limited current to its output and will not source any current. E1 is a differential copying device (voltage source) such that the voltage across its output terminals is defined such that it is equal to the differential voltage between its (+) and (-) input terminals.

In principle circuit comprises of two functional blocks:

1.      An “open circuit” current limiting function achieved by copying the gate-source voltage generated across M1 onto the gate-source of the combination of M2 and M3. The circuit will be in this condition for all output currents significantly above the transition current defined by the voltage developed across R and the reference voltage Vlevel. In this conditio...