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A Vestigially Extrapolated Via For Local Interconnection in MRAM FET Fabrication

IP.com Disclosure Number: IPCOM000028521D
Original Publication Date: 2004-May-18
Included in the Prior Art Database: 2004-May-18
Document File: 6 page(s) / 119K

Publishing Venue

IBM

Abstract

The 1T1J (1 Transistor and 1 Tunnel Junction) architecture for Magnetic Random access memories required Back-End of Line integration of Magnetic Tunnel Junctions (MTJ) to CMOS transistors. A local interconnect straps and contact via connect the tunnel junction to the CMOS front end. The via level is critical in that it typically precedes MTJ stack deposition and hence becomes the substrate for the Tunnel Junction (TJ). Reliability and cost could be improved by an alternate mechanism. We propose to that effect, an integration scheme where the via is constructed after the MTJ module.

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A Vestigially Extrapolated Via For Local Interconnection in MRAM FET Fabrication

Background

     Magnetic Random Access Memories (MRAM) is promising as a universal memory technology. MRAM processing involves modifying the standard Back End of Line (BEOL) processing to insert Magnetic Tunnel Junctions (MTJ) between two successive wiring levels. The cross-point cell (XPC) is one of the architectures pursued for MRAM. Gallagher et al. disclose such architecture, where MTJs are placed at the intersection of perpendicular word and bit lines [1]. The individual bits are addressed for both Read and Write operations by selecting the bit and wordlines that intersect over the TJ. In contrast, the one transistor-one TJ (1T1J, also know as FET) architecture uses a select transistor for the Read operation while maintaining the same write address scheme as the XPC [2]. Fig.1 shows a schematic cross-section of both architectures. This isolation of read and write paths at the wordline level (Lower metal) greatly improves the Read operation in the FET architecture over the XPC. Sitaram et al. teach an integration scheme where a local interconnect metal level connects the MTJ to the underlying electronics through a via level [3]. The additional modules involved in defining the local interconnect and the contact via makes the FET more expensive to fabricate than the XPC architecture.

Prior Art for contact Via

     The contact via connects the local interconnect strap to a Landing Pad (LP). As described in prior literature, this interconnect via could either be shallow i.e. only span the thin dielectric that isolated the Write Wordline (WL) from the Tunnel Junction [3] (see fig. 1(a)) or a deep via that spans the isolation dielectric and the inter-level dielectric (ILD) around the WL and lands on a metal level below the WL [4] (see fig. 2). Both these techniques have their respective pros and cons. The deep via is more complex for etch and metal fill but allows for better scaling of MRAM devices compared to the shallow via.

Vestigially extrapolated Via

     We propose herein an alternative paradigm for the contact via construction. Whereas prior art requires that the vias be constructed before the MTJ stack deposition, we claim a technique where the via is constructed after the TJ and local interconnect etch levels. Figure 3(a) illustrates such a via. The Tunnel Junction is enclosed between the wordline and bitline constructed in the n and n+1th metallization levels. A via is etched from the top of ILD enclosing the bitline (Mn+1) to a landing pad constructed in the same metallization level as the wordline (Mn) in a preferred embodiment. The via etch traverses through the Mn+1 ILD, any hardmask used for the local interconnect etch and the isolation dielectric. The via

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makes lateral contact along its periphery to the local interconnect strap and at its lower end to the landing pad. Since the segment of the via above the interconnect strap is vestigial,...