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System and Method for Developing Non Uniform Memory Architectures (NUMA) Testing Procedures and Applications

IP.com Disclosure Number: IPCOM000028719D
Original Publication Date: 2004-May-27
Included in the Prior Art Database: 2004-May-27
Document File: 9 page(s) / 187K

Publishing Venue

IBM

Abstract

With the advent of (NUMA) Non Uniform Memory Architectures, increasing complexity is affecting high-end servers. Testing, debugging, and stressing within a NUMA server needs to address the high-speed cache coherent system interconnects with emphasis on processors to local and non local memory. With the advent of (NUMA) Non Uniform Memory Architectures, increasing complexity is affecting high-end servers. Testing, debugging, and stressing within a NUMA server needs to address the high-speed cache coherent system interconnects with emphasis on processors to local and non local memory.

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System and Method for Developing Non Uniform Memory Architectures (NUMA) Testing Procedures and Applications

    Non Uniform Memory Architecture (NUMA) utilizes an ACPI table's Static Resource Affinity Table (SRAT); this information describes the Proximity Domain of each Processor and Memory Range. The Proximity Domain corresponds to the locality of Processors and Memory. Using the information of the Proximity Domain, Processors and Memory can be corresponded to each other as being present on the same Node. Nodal Information can now be used to create Interconnect Cross Nodal Tests from Processors in one proximity to Memory Ranges in another.

Processor 01

Processor 00

Processor 11

Processor 10

Processor 02

Processor 03

Processor 12

Processor 13

Memory Controller

Memory Controller

Memory Range 02

Memory Range0 1

Memory Range 12

Memory Range 11

Memory Range 00

Node / Proximity 0

I/O - 0

I/O - 1

Memory Range 10

Node / Proximity 1

   Nodal Interconnections

Processor 21

Processor 20

Processor 31

Processor 30

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Processor 32

Processor 33

Memory Controller

Memory Controller

Memory Range 32

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I/O - 3

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Node / Proximity 3

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(Figure 1 - Four Node NUMA Example)

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    Interconnects are tested by selecting two different nodes, a Processor Node and a Memory Node. The Processor Node has the processors that will run a write, read, and compare test on its target memory. The Target Memory is housed on the Memory Node.

    Using a NUMA Example of a four node system, these are the corresponding Processor-Memory Node Combinations:

  Combination Processor Node Memory Node 0 0 0 1 0 1 2 0 2 3 0 3 4 1 0 5 1 1 6 1 2 7 1 3 8 2 0 9 2 1 10 2 2 11 2 3 12 3 0 13 3 1 14 3 2 15 3 3 (Table 1 - Four Node NUMA Example, Processor Node to Memory Node)

    Sixteen total combinations of processor node to memory node paths. Each combination traverses a unique path from the Processor Node to the Memory Node with no duplicates.

  Combination Processor Node Memory Node 0 0 0 5 1 1 10 2 2 15 3 3 (Table 1 - Four Node NUMA Example, Processor\Memory Node Optimal Cases)

    Combinations 0, 5, 10, and 15 are cases wherein the Processor Node and Memory Node referenced are the same. When the Processor and Memory Node are the same, this is an optimal case in which Nodal Interconnects are not passed through.

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Processor 01

Processor 00

Processor 11

Processor 10

Processor 02

Processor 03

Processor 12

Processor 13

Memory Controller

Memory Controller

Memory Range 12

Memory Range 11

PCI 12

Memory Range 10

PCI 11

PCI 10

Node / Proximity 1

Memory Range 02

Memory Range0 1

PCI 02 Memory Range 00

PCI 01

PCI 00

Node / Proximity 0

   Nodal Interconnections

Processor 21

Processor 20

Processor 31

Processor 30

Processor 22

Processor 23

Processor 32

Processor 33

Memory Controller

Memory Range 22

Memory Range 21

PCI 22

Memory...