Browse Prior Art Database

Mirror the front side bus for failover

IP.com Disclosure Number: IPCOM000028735D
Original Publication Date: 2004-May-28
Included in the Prior Art Database: 2004-May-28
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Abstract

Front side bus failover within a North Bridge.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 2

Mirror the front side bus for failover

     The North Bridge will contain two FSB agents. This will allow for two separate FSB's to be connected up to the North Bridge. When coming out of reset, the North Bridge can come up in either mirrored mode or non-mirrored mode. In non-mirrored mode it will treat each FSB independently, treating each as a separate cluster or processors.

     Some FSB specification allow for multiple processors on one bus, while other allow for only one. This invention is independent of what FSB specification is being used, but will focus on Intel processors because that is the one most familiar to the authors. No matter which FSB specification the North Bridge is designed to be used with, the two FSB's must be balanced. For example, if the FSB allows for up to four processors to be attached, but the primary FSB only has 3 processors installed then the secondary FSB must have exactly 3 processors installed. The cache size must also be the same for all processors to maintain synchronization.

     If the North Bridge comes out of reset in mirrored mode, then one FSB will be the primary bus and one will be the secondary bus. It does not matter which bus becomes primary and which one is secondary. When a processor comes out of reset, it will start fetching code from a known location. For Intel processors, this is a default location of 0xFFFFFC00. For other processors, such as PowerPC processors, an external agent (such as a service processor) typically sets u...