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Rendezvous & Wakeup Mechanisms for Platform Management Interrupt (PMI) Handler Disclosure Number: IPCOM000028737D
Original Publication Date: 2004-May-28
Included in the Prior Art Database: 2004-May-28
Document File: 2 page(s) / 11K

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Intel's Itanium Product Family (IPF) processor architecture uses Platform Management Interrupt (PMI) to handle system management events independent of the Operating System (OS). It is also similar to the System Management Interrupt (SMI) in x86 processor architecture. Intel's System Abstraction Layer (SAL) defines a rendezvous & wakeup mechanisms for Machine Check Exception (MCE) handler. However, Intel doesn't define a rendezvous & wakeup mechanisms for the PMI handler. The rendezvous mechanism is needed to quiesce the system before handling the event, while the wakeup mechanism is needed to resume after handling the event.

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Rendezvous & Wakeup Mechanisms for Platform Management Interrupt (PMI) Handler

     The PMI is a highest priority interrupt in IPF architecture, just like SMI in the x86 architecture. The PMI is disabled upon entry to the PMI handler by the processor to prevent nesting, just like any other regular interrupts. Since, PMI handler has the highest priority, it doesn't need to re-enable the PMI, as soon as possible, after saving interruption resources. So, the nested PMIs are blocked, while the PMI handler is running. All the nested PMIs are seen as a single pending PMI upon reenabling the PMI, to ensure that the subsequent PMI events are not lost. However, in order to safely execute the PMI handler, it is also necessary to ensure that the system is quiesced, so that there is no conflict in accessing the system resources, between the processor running the PMI handler & all other processors in the system. So, a rendezvous & wakeup mechanism is needed for the PMI handler, to ensure that all other processors in the system are in the PMI rendezvous spin loop, while any one of the processors in the system handles the PMI event.

     Following is the pseudo code for the PMI handler for all processors in the system, which highlights the rendezvous & wakeup mechanism for the PMI handler, described in the summary above:
1. The processor enters PMI handler due to some event.
2. Wait until PMI Lock is acquired by the processor, to support simultaneous PMIs in multiple processors.
3. Check if PMI in Progress is set for the processor? If yes,

          Check if PMI was caused by Rendezvous Vector (rv = 1, 2 or 3) or Rendezvous Requested is set for the processor If yes,

spin=true retry=false

retry=false Also, set PMI in Progress for all processors in the system.

4. Release the PMI Lock, to allow other processors in the PMI handler to also enter the spin loop below.
5. If spin or retry, Set Rendezvous in Progress for the processor. Wait until PMI in Progress for the pr...