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Method for cache tag buffer arrays

IP.com Disclosure Number: IPCOM000028871D
Publication Date: 2004-Jun-04
Document File: 8 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for cache tag buffer arrays. Benefits include improved functionality, improved performance, and improved power performance.

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Method for cache tag buffer arrays

Disclosed is a method for cache tag buffer arrays. Benefits include improved functionality, improved performance, and improved power performance.

Background

              Instruction and data caches have long been used in memory systems of general-purpose processors to improve performance. Multiple levels of caching enable systems with fast microprocessors to have a large amount of low-cost memory. Caches are used in digital signal processors (DSPs) and other embedded processors to bridge the performance gap between fast processors and slower low-cost memory. The organization of these caches have significant impact on the efficiency and power consumption of systems built with these processors. N-way set associative caches are the preferred choice of cache organization compared to a direct-mapped cache due to their better hit rates (see Figure 1).

              The n-way set associative caches require extra hardware for associative look-up of tags, which use power. For example, consider a program kernel. Assuming that the cache is cold, the number of tag array reads is 4*2*256=2048. The number of tag comparisons is 4*2*256=2048 (see Figure 2).

              Some embedded processors like digital signal processors (DSPs) have two data buses and data caches that support concurrent accesses by providing two ports. A dual-port cache is typically implemented with several memory banks that provide concurrent access to different banks. Accessing the same bank incurs a delay to enable sequential access. Typical algorithms read two distinct arrays, operate on them, and produce a result.

General description

              The disclosed method is cache tag buffer arrays (CTBAs) that store the most recently read cache tags in an array of tag buffers. The method eliminates the requirement to read identical tags on an access to the same cache line. This procedure reduces the hardware complexity but imposes a restriction on the effective memory access patterns.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to enabling CTBAs

•             Improved performance due to eliminating the delay for sequential access

•             Improved performance due to reducing the number of tag array reads and tag compares

•             Improved performance due to reducing the comparator size 20 bits to 4

•             Improved power performance due to reducing the power consumed by the set-associative level 0 (L1) cache

Detailed description

              The disclosed method is cache tag buffer arrays (CTBAs). The method works due to the temporal and spatial locality of data accesses in programs. Each tag buffer stores the cache tag and the corresponding cache way where the line is stored in the data array. When an access hits in the tag buffer, the way information is used to access the data array, avoiding cache tag array access and saving power. The CTBA is indexed by the index of the address...