Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Fast High Voltage Level Shifter

IP.com Disclosure Number: IPCOM000028955D
Original Publication Date: 2004-Jul-25
Included in the Prior Art Database: 2004-Jul-25
Document File: 5 page(s) / 55K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The following text presents an idea which provides an improved voltage level shifter for a fast logic level translation without increasing circuit complexity and current consumption. Fig. 1 shows a standard DC level shifter, generally used for such low quiescent current application. A logic signal from the low voltage rails VSS and VDD is transferred to a translated switching signal disposed between the VSSH and VDDH rails. As illustrated in the next picture, Fig. 2 (left and right), the translation delays depend mainly on the charging-discharging time of the parasitic capacitors. An increment of the N1-2 size, in order to improve the corresponding transconductance, can optimize the switch from H to L. As a result, the related drain to substrate parasitic capacitor C3 increases, slowing down the other transition L to H.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 5

S

Fast High Voltage Level Shifter

Idea: Riccardo Pittassi, IT-Padova

The following text presents an idea which provides an improved voltage level shifter for a fast logic level translation without increasing circuit complexity and current consumption. Fig. 1 shows a standard DC level shifter, generally used for such low quiescent current application. A logic signal from the low voltage rails VSS and VDD is transferred to a translated switching signal disposed between the VSSH and VDDH rails. As illustrated in the next picture, Fig. 2 (left and right), the translation delays depend mainly on the charging-discharging time of the parasitic capacitors. An increment of the N1-2 size, in order to improve the corresponding transconductance, can optimize the switch from H to L. As a result, the related drain to substrate parasitic capacitor C3 increases, slowing down the other transition L to H.

The use of a larger device for P1-P2, to reduce the equivalent on state channel resistor, increments the delay during the turn on phase of the corresponding gate. The gate to source capacitor Cgs of the cascade p-channel device must be considerable taken into account, as one of the bigger parasitic capacitance. The simple size trimming of this standard signal translator, just to obtain an optimum trade off between the two transitions, can only improve the intrinsic transition speed limit.

To avoid the aforementioned problem, a solution is proposed in the following: Firstly the cell depicted in Fig. 1 has to be designed with larger width channel N1-N2 MOS devices (Metal-Oxide Semiconductor) and smaller P1-P2 transistors to achieve the fastest H to L transition. Secondly an additional p-channel transistor P5, with the necessary W/L ratio to get a low equivalent RDS-on resistor, must be placed in parallel to P1 (cf. Fig. 3). Its gate is driven by a single pulse, generated by the H to...