Browse Prior Art Database

Logical Multiple Processor Power Saving Method

IP.com Disclosure Number: IPCOM000028975D
Original Publication Date: 2004-Jun-10
Included in the Prior Art Database: 2004-Jun-10
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Abstract

Disclosed is a hardware circuit to achieve efficient power saving for multiple processors which share resources such as external clock generator and voltage regulator.

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Logical Multiple Processor Power Saving Method

In PC (Personal Computer) industry, high frequency processor and its sophisticated micro code technology now enable to fully utilize a processor's internal resources by operating a physical processor as logical multiple processors for software. "Intel(*1) Hyper-Threading Technology" is one of typical examples of the technology. In addition, progress of chip integration technology also introduces possibility of having multiple physical processors within a single die. With these technologies, more and more system throughput can be expected on operating systems which support multiple processors.

These multiple processors share resources such as single external clock generator and single voltage regulator. For mobile PC, it is one of important technologies to reduce power consumption by programming these resources. Current operating systems do no support power saving methods for these multiple processors, thus it is required to have workaround methods by system BIOS or device drivers in these cases. For Windows(*2) systems in most cases, system BIOS can provide the software workaround method by using system management interrupt (SMI) in general.

However, SMI workaround method forces much execution overhead, especially in multiple processor environment. So the method is not suitable to control power saving in efficient timing. This disclosure explains a method to solve this problem with a new hardware circuit which achieves efficient power saving for these multiple processors.

On Intel(*1) architecture processor or compatible processor, special cycle is generated to front side bus connected to the processor, when system software executes HLT (halt execution) instruction to put processor power state[1] to C1[1] state to reduce power consumption. The disclosed power saving method provides a new hardware circuit in chipset connected to the front side bus. This new hardware circuit checks halt state of all logical processors by monitoring special cycle generated by HLT instruction execution, then programs C2[1], C3[1] processor power states if all logical processors are in halt state. In this way, the disclosed new hardware circuit achieves efficient processor power saving without software workaround methods.

Fig.1 shows...