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CIRCUIT DESIGN FOR ESD ROBUST PMOS OUTPUT BUFFER

IP.com Disclosure Number: IPCOM000029048D
Original Publication Date: 2004-Jun-14
Included in the Prior Art Database: 2004-Jun-14
Document File: 5 page(s) / 73K

Publishing Venue

Motorola

Related People

Michael Khazhinsky: AUTHOR [+3]

Abstract

An ESD protection circuit and a method for providing ESD protection are presented. In some embodiments, a P-channel transistor, which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the P-channel transistor is to maximize the Vt1 of the P-channel transistor. Vt1 is the drain-to-source voltage point at which parasitic bipolar action is initiated, generally resulting in immediate physical damage in the device.

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Circuit Design for ESD Robust PMOS Output Buffer

Michael Khazhinsky, James Miller, Bernie Pappert

Abstract

An ESD protection circuit and a method for providing ESD protection are presented.  In some embodiments, a P-channel transistor, which can be ESD damaged, is selectively turned on and made conducting.  The purpose of turning on the P-channel transistor is to maximize the Vt1 of the P-channel transistor.  Vt1 is the drain-to-source voltage point at which parasitic bipolar action is initiated, generally resulting in immediate physical damage in the device.

Description

Our approach provides an ESD robust output buffer which has the advantages of compact layout area and minimal impact on electrical performance during normal operation.  We have designed multiple circuits to drive the gate of the PMOS output driver to the full I/O pad voltage during a detected ESD event (see FIG. 1). Therefore, during ESD, the fragile PMOS gate and drain are shorted together. We call this "PMOS-on" or “hot gate” biasing. It turns out that this bias condition greatly reduces the impact ionization at the drain junction due to the reduced drain to gate field and, therefore, increases Vt1.

During the ESD event, the gate bias circuit (FIG. 1A) provides a bias voltage on the gate of PMOS output buffer.  ESD current flow through the NMOS output buffer insures a significant potential difference between I/O pad and OVSS.  If the local OVSS voltage exceeds the I/O pad voltage by greater than an N-channel transistor threshold voltage, the N-channel transistor ESD_DETECTOR_1 will turn on and work to decrease node A to the I/O pad voltage.  Resistor r0 is sufficiently resistive so that, once N-channel transistor ESD_DETECTOR_1 is turned on, it can easily pull node A to near the I/O pad voltage.  N-channel transistor M4 and P-channel transistor M3 form a CMOS inverter such that, when node A is lowered to the I/O pad voltage, the gate terminal of N-channel transistor M6 is pulled to OVDD.  This turns on N-channel transistor M6, which then pulls pdrv node down to the same voltage as I/O pad.  In this manner, during an ESD event, the biasing circuit provides a bias voltage on the gate of P-channel buffer, which is substantially equal to the bias voltage at I/O pad. Therefore, during an ESD event detected by the ESD event detection circuit, PMOS output buffer is biased such that its gate voltage (Vgate) is approximately equal to its drain voltage (Vdrain).  The biasing circuit may also include a transmission gate (not shown) which serves to decouple the gate of P-channel transistor from other logic on IC which may interfere with the operation of biasing circuit during the ESD event. If a separate ESD event triggering signal ‘esd_trig’ is available on chip, the Gate Bias Circuit can be omitted (FIG. 1B).

To prevent turn-on of the parasitic diode associated with the P-well of M6, a s...