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Method for an event-triggered timer with glitch reduction

IP.com Disclosure Number: IPCOM000029143D
Publication Date: 2004-Jun-16
Document File: 3 page(s) / 34K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an event-triggered timer with glitch reduction. Benefits include improved functionality.

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Method for an event-triggered timer with glitch reduction

Disclosed is a method for an event-triggered timer with glitch reduction. Benefits include improved functionality.

Background

              Most large time delay circuits are based on a resistance capacitance (RC) delay element or an asynchronous clock source with a digital counter to acquire a delayed version of the original signal. These designs are either extremely sensitive to process control or have an uncertain time step due to their asynchronous nature. If the timer is capable of noise filtering, an extra glitch-reduction circuit must be added.

              One conventional solution uses a long inverter chain to form a large delay. If the required delay is long, many transistors are required, which increases layout space and consumes more dynamic and static power. Additionally, this solution has no glitch reduction capability (see Figure 1).

 

              Another solution uses resisters and capacitors. The resisters are formed by a stack of positive-channel metal oxide semiconductor (PMOS) transistors. The capacitors are formed by metal oxide semiconductor (MOS) transistors (either PMOS or NMOS) or metal to achieve long delays. This solution not only requires a weak pull-up PMOS stack, which is very sensitive to process control, but a large capacitance. The MOS or metal capacitor design is subject to process control restrictions or requires an extremely large layout space. This solution has no glitch reduction capability (see Figure 2).

              A conventional method, which is not illustrated, uses a free running clock generator to power up a digital counter. The problem with this design is that the timer-out assertion is not synchronized to the event, making the logic state unrepeatable and unusable for most applications. An extra noise-filtering circuit is required for glitch reduction.

General description

      The disclosed method is a synchronized event triggered timer that is extremely compact and is capable of noise filtering. The method uses an event-triggered double reset ring oscillator in conjunction with the digital counter to achieve a less process...