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Method for a variable-bump BGA package

IP.com Disclosure Number: IPCOM000029150D
Publication Date: 2004-Jun-16
Document File: 4 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a variable-bump ball grid array package (BGA). Benefits include improved functionality and improved performance.

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Method for a variable-bump BGA package

Disclosed is a method for a variable-bump ball grid array package (BGA). Benefits include improved functionality and improved performance.

Background

              An industry trend is for the BGA pitch to become smaller. As a result, the solder joint reliability of the second-level interconnect decreases because the stand-off height between the package and the board becomes less than for larger-ball components. The smaller standoff decreases the flexibility of the solder joint during temperature cycling loading, resulting in solder joint cracking sooner in the component’s life cycle. This problem typically occurs under the die where the coefficient of thermal expansion (CTE) is the highest. To increase solder joint reliability, some packages require a larger ball size, which is difficult to assemble in fine pitch. Others use more compliant material, which increases the cost of the package, or underfill epoxy at the second-level interface, which increases the assembly cost.

      Conventionally, the use of large solder bumps on BGAs and chip-scale packages (CSPs), which limits the possible reduction in pitch. The larger size bumps can impact assembly yield due to the size of the ball (see Figure 1).

      Epoxy underfill is used to provide reliable solder joints. This process requires additional equipment in the board assembly shop and adds significant cost to the BGA assembly process. Additionally, rework in this location is not possible (see Figure 2).

      BGA designs use expensive substrate material and an interposer layer to reduce the stress on the joints. This approach increases package cost.

General description

      The disclosed method includes a stepped substrate and variable-sized solder balls on BGA or CSP grid array packages. The method increases the stand-off height of a package and improves the solder joint reliability under the die of the second-level interface between the package and the printed circuit board (PCB). Additionally, this method improves power delivery and the electrical performance of the chip.

              The key elements of the method include:

•             Package with stepped substrate and two sizes of solder balls

•             Large size ball under the die shadow

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to providing a fine pitch BGA and larger solder balls where ad...