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Method for dual diagonally split dies for I/O fan-out count optimization

IP.com Disclosure Number: IPCOM000029154D
Publication Date: 2004-Jun-16
Document File: 2 page(s) / 23K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for dual diagonally split dies for input/output (I/O) fan-out count optimization. Benefits include improved functionality and improved performance.

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Method for dual diagonally split dies for I/O fan-out count optimization

Disclosed is a method for dual diagonally split dies for input/output (I/O) fan-out count optimization. Benefits include improved functionality and improved performance.

Background

      As the I/O count scales higher, changes in chip design must occur. The die size can be increased, which is indicated by a dotted line for a larger die outline (see Figure 1). If die size is not increased, rows can be added to the I/O ring. In this case, the minimum trace width design rule may have to be revised to allow more I/O rows. Alternatively, a routing layer may be added to the inside of the package. Conventionally, the die size is increased or the package layer count is increased.

General description

      The disclosed method increases the I/O fan-out count without increasing the die size. Functional blocks are added into a die to provide additional features, such as graphics, computing, and wireless integration capability. As a result, additional I/O connections are required. The disclosed method uses two triangular dice, which provide two hypotenuses lengths (one on each die) with multiple I/O connections without increasing the die size or package layer count.

              The key element of the method includes two diagonally split triangular dice.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to increasing the I/O count without incr...