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Method for a hybrid ball/pin grid array package with a connector and very high speed I/O

IP.com Disclosure Number: IPCOM000029155D
Publication Date: 2004-Jun-16
Document File: 4 page(s) / 181K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a hybrid ball/pin grid array package with a connector and very high speed input/output (I/O). Benefits include improved performance.

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Method for a hybrid ball/pin grid array package with a connector and very high speed I/O

Disclosed is a method for a hybrid ball/pin grid array package with a connector and very high speed input/output (I/O). Benefits include improved performance.

Background

              The conventional device package includes high-loss vertical structures, such as vias, plated through holes (PTHs), and solder balls, which introduce mismatch loss (see Figure 1).

              To minimize mismatch loss from vertical structures, a thin-core package, which shortens the vertical transmission path, is used. However, a mismatch point occurs between the well-referenced microstrip (or stripline) structure and the unmatched vertical structures (see Figure 2).

              The package model with vias, PTHs, and solder ball structures shows high loss. Transmission loss is –1 dB at 20 GHz, and the loss roll off at 50 GHz to –15 dB at 80 GHz. Most of the energy is reflected at the point of mismatch between the trace and via, via and PTH, and the PTH and solder ball (see Figure 3).

General description

      The disclosed method is optical packaging with a connector and very high frequency I/O. The disclosed method includes a connector to provide an alternative method for ball-out to the microstrip routing. Unoptimized vertical transmission structures are eliminated. The method ensures minimum mismatch when the I/O signals propagate from the well-referenced microstrip or stripline transmission line on a package to a transmission line on a board.

Advantages

              The disclosed method provides advantages, including:

•             Improved performance due to optimizing the package trace to the motherboard by eliminating high-loss mismatched vertical structures for high-speed I/O

Detailed description

              The disclosed method incorporates connector technology into a typica...