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Method for plane-referencing packages for high-speed signaling via power and signal decoupling

IP.com Disclosure Number: IPCOM000029160D
Publication Date: 2004-Jun-16
Document File: 4 page(s) / 146K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for plane-referencing packages for high-speed signaling via power and signal decoupling. Benefits include improved functionality and improved performance.

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Method for plane-referencing packages for high-speed signaling via power and signal decoupling

Disclosed is a method for plane-referencing packages for high-speed signaling via power and signal decoupling. Benefits include improved functionality and improved performance.

Background

      A multilayer high-speed package is required for CPU and communication chips when high-quality signal integrity. The solution must have reduced capacitance.

      Conventionally, the problem is solved by routing single-ended or differential lines on the surface of the package and making via transitions all the way to lands or solders balls. Typically, treatment for the vertical-path improvements is widening the size of a void to reduce parasitics between the signal lines and power/ground planes. This treatment is applied for both single-end and differential signaling and can be combined with a stitching-via design. Another approach is to reduce the core thickness of packages.

      Signal escaping from package dice using flexible printed circuit boards (PCBs) has been proposed, but the change is quite a revolutionary approach. Many conventional package designs place voids between the power and signal paths to prevent shoring. No other treatments are available except widening the void dimensions. In some low-density interconnect (LDI) applications, adding stitching vias and plated through holes (PTHs) near the signal improves signal performance. However, these solutions do not provide significant improvement because, typically, the power and ground planes are placed alternately. Their sensitivity drops as the power path crosses the ground planes. Additionally, the cost of packages is increased as the number of additional drillings, plugging, and trimming process increases (see Figure 1).

General description

      The disclosed method is an integrated circuit (IC) package layout for high-speed digital applications where reducing the interplane parasitics (capacitance) is the key element of achieving high quality signal integrity. The method completely decouples the power planes from high-speed input/output (I/O) signals and reconfigures all conducting planes for signal referencing. The disclosed method can be applied to conventional ceramic and organic package design to improve high-speed I/O performances significantly at n...