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Method for generating CPU VTT power-good and VR-enable signals

IP.com Disclosure Number: IPCOM000029240D
Publication Date: 2004-Jun-18
Document File: 2 page(s) / 62K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for generating CPU VTT power-good and VR-enable signals. Benefits include improved functionality.

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Method for generating CPU VTT power-good and VR-enable signals

Disclosed is a method for generating CPU VTT power-good and VR-enable signals.  Benefits include improved functionality.

Background

              Conventional designs used an integrated low drop out regulator that generated this signal internally. This solution is no longer an option. Other attempts at this circuit failed to meet the rise time.

Description

              The disclosed method senses the voltage of an input rail (VTT) and provides an active-high power-good output signal with a rise time of 150 ns or faster. The output signal should be the same voltage as the input signal and delayed by at least 1 ms. The method is a very important function and circuit for power sequencing. Failure to meet the specifications may lead to system instabilities or processor damage.
              The disclosed method includes a circuit (see Figure 1). Resistors R1 and R2 set the trip point of about 90% of the input voltage. The impedance of R1, R2, and the 1µF cap (C1) results in about 2.4 ms delay between the input signal and the output signal.
              The challenge in this circuit is to create a fast rising edge (<150 ns) using a slow input rail as the input and the source of the output. Three gain stages, designated as Q1, Q2, and Q3, produce a fast rising edge and an output state, Q4 (positive-negative-positive), which are tied directly to the VTT. The result is a rising edge of about 40 ns.

              The output signal i...