Browse Prior Art Database

Improved PCI-Express Receiver

IP.com Disclosure Number: IPCOM000029460D
Original Publication Date: 2004-Jun-29
Included in the Prior Art Database: 2004-Jun-29
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Abstract

The circuit described here makes use of a common gate stage to solve the problem of detecting differential signals having their common mode biased at ground in a single power supply environment, as is the case with the PCI-Express interface. It allows for the use of higher performance N-channel devices and takes advantage of the inherently low source input impedance to match the 50 ohm interface.

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Improved PCI-Express Receiver

The PCI-Express Serial Interface requires 50 ohm terminating resistance from each differential input to ground, which forces the input signal to be biased close to ground. Since most logic chips only have positive power supplies (no negative), the conventional diff amp configuration would have to be designed with PMOS devices which tend to have poorer bandwidth than NMOS devices. In addition, the outputs from these PMOS devices generally need to be level shifted high to interface to succeeding circuits resulting in degraded performance.

     The scheme described here uses an NMOS common gate diff amp configuration, which has the following advantages: It uses faster NMOS devices.

It provides the required level shift from the low level input signal centered near

ground to the output signal biased around Vdd/2. The source input of the NMOS devices are low impedance which works well with the

50 ohm termination requirement. This circuit is much simpler. It consists of only one stage versus two or three in

other schemes.

     The differential input signals are brought in to Pinput and Ninput. Coupling capacitors C1 and C2 are part of the board wiring as required by the PCI-Express specification (see Figure 1). The 65 ohm termination resistors, RTP and RTN, are in parallel with the source resistance of NMOS T1 and NMOS T2. This sources resistance is determined by the NMOS device characteristics and the load resistors and is just over 200 ohms. The re...