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Integration of a Large Scale MOS Transistor Array for Reliability Evaluation of Sub-100nm MOS Technologies

IP.com Disclosure Number: IPCOM000029469D
Original Publication Date: 2004-Jul-25
Included in the Prior Art Database: 2004-Jul-25
Document File: 2 page(s) / 153K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Transistor arrays can be used as a test structure for the dielectric reliability assessment of MOS (Metal-Oxide Semiconductor) devices used in CMOS (Complementary MOS) technologies. The transistor array allows to significantly increase the number of test structures accessible through a fixed number of probe pads (e.g. 25). To further increase the device density, a 'large scale MOS transistor array' is introduced as a reliability test structure for sub-100nm MOS technologies. The need for such a sophisticated test structure is based on the fact that breakdown detection on ultra-thin gate dielectrics is limited to small area (< a few ┬Ám2) test structures due to the large gate leakage current. On the other hand, for an extrinsic reliability assessment, the total test area has to be in the order of ATest~0.01cm2 for an extrinsic defect density of D<100cm-2. In addition, the post breakdown gate to channel conductance and its impact on the MOSFET (MOS Field-Effect Transistor) device characteristic are of crucial importance from circuit reliability point of view. To investigate and guarantee post breakdown circuit functionality of sub-100nm CMOS technologies, degradation measurements on large scale MOS transistor arrays are a viable approach. In Figure 1 an elementary cell in such a large scale transistor array is shown schematically. The cell consists of the Device Under Test (DUT) with a 'thin' gate dielectric and three select transistors manufactured with a 'thick' gate dielectric. The device under test is selected when the select transistor for the gate terminal (STG), and the source (STs) and drain (STD) terminals are enabled using the appropriate select bias (VG_S and VD/S_S). To minimize the impact of series resistance during a stress experiment, the design of the select transistors has to be optimized (channel length, width,...). Furthermore, when large transistor arrays are fabricated, minimizing the off-currents is also a critical issue.

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Integration of a Large Scale MOS Transistor Array for Reliability Evaluation of Sub-100nm MOS Technologies

Idea: Dr. Andreas Kerber, DE-Munich; Dr. Martin Kerber, DE-Munich

Transistor arrays can be used as a test structure for the dielectric reliability assessment of MOS (Metal-Oxide Semiconductor) devices used in CMOS (Complementary MOS) technologies. The transistor array allows to significantly increase the number of test structures accessible through a fixed number of probe pads (e.g. 25). To further increase the device density, a 'large scale MOS transistor array' is introduced as a reliability test structure for sub-100nm MOS technologies. The need for such a sophisticated test structure is based on the fact that breakdown detection on ultra-thin gate dielectrics is limited to small area (< a few µm2) test structures due to the large gate leakage current.

On the other hand, for an extrinsic reliability assessment, the total test area has to be in the order of ATest~0.01cm2 for an extrinsic defect density of D<100cm-2. In addition, the post breakdown gate to

channel conductance and its impact on the MOSFET (MOS Field-Effect Transistor) device characteristic are of crucial importance from circuit reliability point of view. To investigate and guarantee post breakdown circuit functionality of sub-100nm CMOS technologies, degradation measurements on large scale MOS transistor arrays are a viable approach.

In Figure 1 an elementary cell in such a large scale transistor array is shown schematically. The cell consists of the Device Under Test (DUT) with a 'thin' gate dielectric and three select transistors manufactured with a 'thick' gate dielectric. The device under test is selected when the select transistor for the gate terminal (STG), and the source (STs) and drain (STD) terminals are enabled using the

appropriate select bias (VG_S and VD/S_S). To minimize the impact of series resistance during a stress

experiment, the design of the select transistors has to be optimized (channel length, width,...). Furthermore, when large transistor arrays are fabricated, minimizing the off-currents is also a critical issue.

A simplified schematic drawing of the elementary cell is shown in Figure 2, where the control inputs are labeled as VG_S and VD/S_S, an...