Browse Prior Art Database

Process to Reuse Array Building Blocks

IP.com Disclosure Number: IPCOM000029506D
Original Publication Date: 2004-Jul-01
Included in the Prior Art Database: 2004-Jul-01
Document File: 4 page(s) / 53K

Publishing Venue

IBM

Abstract

A process is described that is used to facilitate the reuse of peripheral circuits when creating sram arrays for a technology test chip.

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Process to Reuse Array Building Blocks

During creation of a chip, many different array cells are used. The cells can vary in size, threshold voltage, orientation, or device count. Each of the cells then must have peripheral circuity created to enable read and write functions. A great amount of time is required to design this peripheral circuitry around each cell.

     A similar process is used to create a test chip to evaluate the technology. Once the test chip has been manufactured, data must be gathered to see how each unique cell performs. Any valid comparison of the cells must somehow eliminate the variation of the surrounding circuits so only the differences in the cells are being measured.

     This process allows quick reuse of the peripheral circuits with varying sized cells. The design time for each array is reduced drastically. Additionally, because the peripheral circuits are exactly the same between the unique cells, the arrays can be distinguished from each other due to the cells alone and not design differences of any other circuits.

     The peripheral circuits are created using the smallest cell dimensions. The schematics and layouts are then created for each cell type. Wire bending layouts are used to align any wires that travel from the cells to the surrounding circuits. Additionally, if the cells are oriented differently, metal layer changes are also made in the wire bending layout. The entire array can now be quickly checked and delivered to manufacturing. I...