Browse Prior Art Database

SERIAL COMMUNICATIONS BAUD RATE FEEDBACK MECHANISM

IP.com Disclosure Number: IPCOM000029766D
Original Publication Date: 2004-Jul-12
Included in the Prior Art Database: 2004-Jul-12
Document File: 3 page(s) / 511K

Publishing Venue

IBM

Abstract

Disclosed is a baud rate tracking mechanism based on data sampling feedback.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 3

SERIAL COMMUNICATIONS BAUD RATE FEEDBACK MECHANISM

This invention provides methods to detect, automatically recover from, and re-adjust baud rate due to transmission errors which occur while receiving a message on a serial interface. The novelty is the method of baud rate adjustment, which seamlessly fits in with the detection and correction aspects o the implementation

       The chip clock frequency is divided by the value in the Baud Rate register to create baud and sampling clocks. The clock phases are locked to the detection of the startbit of each byte in the message. Three data samples are captured near the center of each bit in the message. A majority function is applied to generate the actual data value latched.

       The Error Counter (reset to '0' at the start of each message) counts the total number of bit sampling errors which occur in the serial data. The Error Counter increments by '+1' each time the three data samples captured for any bit in the received message is other than '000' or '111'. The value in this register is a raw reading of message reliability. A higher count per message indicates more noise on the serial interface. The Error Threshold register may be adjusted to inhibit message acknowledge based on the level of noise detected (see Figure 1).

       The Baud Too Fast, Baud Too Slow, and Data Noise counters are reset to '0' at the start of each message received. The conditions for incrementing these registers are tabulated in Figure 2. These registers qu...