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Versatility in Partial Scanning of the Boundary Scan Structure with User Programmable Boundary Scan Macro

IP.com Disclosure Number: IPCOM000029768D
Original Publication Date: 2004-Jul-12
Included in the Prior Art Database: 2004-Jul-12
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Abstract

Many board designs contain both a system controller module with JTAG capabilities along with an external programmable memory device. In order to enable a more efficient board manufacturing process, this invention provides a mechanism by which the external memory device may be programmed by the system controller module through the use of a special JTAG instruction.

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Versatility in Partial Scanning of the Boundary Scan Structure with User Programmable Boundary Scan Macro

Disclosed is an optimized method by which an external programmable memory device may be programmed through the use of a user-defined instruction via a standard JTAG (Joint Test Action Group) interface. The JTAG interface is an interconnect verification approach defined in detail in the Institute of Electrical and Electronics Engineers (IEEE) Standard 1149 documents and implemented on many electronic devices.

Many board designs contain both a system controller module with JTAG capabilities along with an external programmable memory device. Often the external programmable memory device contains the system firmware which is used by a CPU or system controller. This firmware is subject to change over time which challenges the board manufacturing process to ensure that the correct firmware is present on all of the boards. It is thus desirable to initially program the external memory devices via a standard piece of test equipment such as a JTAG Master which may already exist in the manufacturing process. Similarly, Field Service operations could use the JTAG interface for updating the firmware as part of their upgrade or re-furbish process.

Ordinarily, to program the external memory device via the JTAG interface, data is scanned into the chip's boundary-scan register (BSR) cells via the JTAG "SAMPLE/PRELOAD" or "PRELOAD" instruction to define the desired output states. The "EXTEST" instruction transfers these values to the chip's output pins. As a result of repeating the "EXTEST" instruction many times with new data for the memory device pins, the necessary signals on the attached external programmable memory device toggle in a manner that results in the external mem...