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Phase Shifted and Interlaced Memory Interface

IP.com Disclosure Number: IPCOM000029805D
Publication Date: 2004-Jul-13
Document File: 2 page(s) / 34K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that interlaces the routing of two memory channels; it also contains circuitry that fires the two channels 90o out of phase. Benefits include a solution that increases timing and voltage margins.

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Phase Shifted and Interlaced Memory Interface

Disclosed is a method that interlaces the routing of two memory channels; it also contains circuitry that fires the two channels 90o out of phase. Benefits include a solution that increases timing and voltage margins.

Background

Currently, signals next to each other transition at the same time. The resulting crosstalk decreases timing and voltage margins. In addition, this decreases the safety margin of the bus and lowers the highest frequency that the bus can work at.

General Description

In the disclosed method, the data signals on the package are routed in an interlaced pattern (see Figure 1). Since the signals are fired 90o out of phase, a signal in one of the channels transitions next to a signal that is not transitioning. Therefore, the adjacent signals are not impacted by the crosstalk. Since the crosstalk only occurs when adjacent signals have reached a valid high or low, the amount of crosstalk is minimized. In addition, simulations show that the disclosed method can significantly increase timing budgets. The disclosed method will enable a more robust bus to be built.

Advantages

The disclosed method increases timing and voltage margins, while minimizing crosstalk.

Fig. 1

Disclosed anonymously