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Programmable Delay Logic for Fly-By Control Topology

IP.com Disclosure Number: IPCOM000029806D
Publication Date: 2004-Jul-13
Document File: 2 page(s) / 15K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that inserts programmable delay logic (PDL) in the paths of control circuits of different devices. Benefits include increasing the timing margins for systems.

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Programmable Delay Logic for Fly-By Control Topology

Disclosed is a method that inserts programmable delay logic (PDL) in the paths of control circuits of different devices. Benefits include increasing the timing margins for systems.

Background

In a fly-by or a daisy chain topology, the DDR3 address and control signals are routed so that signals reach devices in a chronological order (e.g. the signal reaches device 1 before device 2, device 2 before device 3 etc.). Data routed in a point-to-point topology has the same delay across all data bits (see Figure 1). At DDR3 clock speeds with transfer rates of up to 1600 MT/s, there is a significant delay; this delay crosses clock boundaries on when data is received by the controller from the first device, versus the last device on the channel. A similar delay issue occurs on write transactions.

General Description

The disclosed method inserts PDL in the paths of control circuits of different devices (see
Figure 2). These PDL are programmed to a specific value by a controller at the time of DRAM initialization. The controller detects the device location and programs the delay accurately for control paths for a specific module (see Figure 3). The delay is topology specific. A similar delay logic is required to skew the clocks with controls as well. The logic delay in the path of clocks provides enough setup and hold times for proper latching in the DRAM device.

Advantages

The disclosed method accommodates both fly-by and point-to-po...