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Tuning Read Performance from the Chipset for a Network Interface Controller

IP.com Disclosure Number: IPCOM000029834D
Publication Date: 2004-Jul-14
Document File: 3 page(s) / 32K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that tunes and improves the throughput or latency of a specific network interface controller (NIC) stream for a variety of chipsets. Benefits include enabling the maximum possible read performance from a chipset.

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Tuning Read Performance from the Chipset for a Network Interface Controller

Disclosed is a method that tunes and improves the throughput or latency of a specific network interface controller (NIC) stream for a variety of chipsets. Benefits include enabling the maximum possible read performance from a chipset.

Background

It is difficult to optimize the read performance of the host memory through the chipset for an NIC, because it contains varying traffic patterns. In addition each chipset, or north bridge (NB), has its own unique method of multiplexing the read responses.

NIC read interactions contain important performance operations, such as descriptors

(i.e. commands) fetches, cache fills, and transmit payload fetches. The host memory is the final source for such operations. The chipset sits in the middle to coordinate access from the I/O

device and the processor. The fat “pipe” of the host memory bandwidth is manipulated or multiplexed by the chipset. Figure 1 shows an example of an NIC and an NB in a PCI Express configuration.

General Description

Response sizes from the NB return cache lines. Some NBs combine read responses up to some maximum size (i.e. for PCI-E, the MAX_PAYLOAD register) if the opportunity exists. Some NBs do not interleave between streams (i.e. an independent read request), while some NBs do. The disclosed method’s high-performance NIC has the following advanced capabilities:

§         Creates multiple pipelined read requests, either in the same or different streams to overlap requests for long-round trip paths

§         Re-orders the staging buffer in the host I/F logic to buffer out-of-order responses until they are ready for requesting “clients.” (This capability is quite useful for interleaved NBs.)

Note. Even with the above capabilities, the NIC is not guaranteed to meet its throughput or latency requirements, because the NB’s capability cannot always be closely matched.

Followings are the disclosed methods/algorithms to further tune the read performance.

NIC maintains relevant tuning information in registers that driver or tuning software can write into:

§         Interleave (INTV): NB supports interleaving or not. Default is 0 which implies no interleave.

§         Back-to-back request interval (BBRI):  specify the delay of number of NICs clock cycles.  This is additional delay to NICs best request interval.  Default is 0 which implies no delay. This register is written from BBRIN, BBRII depending on the INTV flag or 0 for no delay.

§         Back-to-back request interval (BBRIN) for INTV = 0:

§         Back-to-back request interval (BBRII) for INTV = 1

§         Recommended back-to-back request size (BBRS): specify the preferred back-to-back request size if different streams exist.

If a NB doesnt support interleave (INTV = 0) between streams then

§         Responses are in order, no mixing between...