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Method for dummy local via generation in 90-nm hierarchical APR designs

IP.com Disclosure Number: IPCOM000030147D
Publication Date: 2004-Jul-29
Document File: 5 page(s) / 41K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for dummy local via generation in 90-nm hierarchical automatic place-and-route (APR) designs. Benefits include improved design functionality and yield, and improved checking and fracture performance.

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Method for dummy local via generation in 90-nm hierarchical APR designs

Disclosed is a method for dummy local via generation in 90-nm hierarchical automatic place-and-route (APR) designs. Benefits include improved design functionality and yield, and improved checking and fracture performance.

Background

              The 90-nm semiconductor process has stringent local via density requirements that are not achievable using conventional methods provided by vendor APR and/or run-set-based tools. Local via density is defined as the density of vias in a given local area, such as 20 µm x 20 µm. Designs are required to meet metal and via density requirements so that higher yields can be achieved in manufacturing. Additionally, the conventional methods, in particular the run-set based ones, can lead to problems during final check and fracture because of the increase in polygon counts.

              A vendor APR tool is conventionally used to add dummy metal lines to a design’s white space. The metal lines are made as long as possible to reduce the polygon count. An increased polygon count increases run time and memory usage for final checks (such as layout vs. schematic and antenna checks) and fracture. Some designs result in a 2-4X increase in run times and have hit the memory limit for fracture after adding dummy metal and vias to a design. The metal lines are tied for proper extraction, to minimize signal integrity (SI) issues, and avoid charge build-up problems during manufacturing. A minimum set of vias are added to complete the tie. The number of vias is insufficient to meet density requirements. No automatic capability is provided to add more vias.

              Run-set based tools are currently used to add small (0.9-µm x 0.9-µm) floating squares of metal and to insert vias between these adjacent-layer metal squares. Leaving the metal floating is not a concern because of their small size. Two key problems occur with this method. An increase in polygon count occurs due to the small squares of metal compared to the APR method of adding long metal lines with larger but fewer polygons. This increase can lead to longer run times and memory size problems during final checks and fracture. Additionally, vias can only be inserted between two adjacent-layer metal squares. In a densely routed design, adding two adjacent layers of metal can be difficult and impossible where power straps occur.

General description

              The disclosed method in conjunction with a vendor APR tool enables local via density requirements to be achieved without detrimental side effects. The increase in the polygon count and the limited via insertion capability from the run-set based method do not occur.

              The key elements of the disclosed method include:

·        Via generation

o       Insertion of vias between adjacent layers of tied (VCC and/or VSS) long dummy metal lines and power straps

o       Interleaving of VCC and VSS tied dummy metal lines under power straps

o       Multiple vias

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