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Target Table For Dependency Tracking For An In-Order Microprocessor

IP.com Disclosure Number: IPCOM000030413D
Original Publication Date: 2004-Aug-12
Included in the Prior Art Database: 2004-Aug-12
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Abstract

A target table is used to perform register tracking to facilitate in-order execution. The main function of the table is to provide the dispatcher an indication of which functional unit is updating a particular register. It also holds the pipe status of the youngest instruction that is updating a particular register. This information is used to determine when a dependent instruction can be dispatched and provides the bypass controls to allow the dependent instruction to grab its operand from the execution pipe.

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Target Table For Dependency Tracking For An In -Order Microprocessor

In an in-order microprocessor design, instructions that are dependent on an older instruction must wait at dispatch for an appropriate number of cycles for their operands to be available. For example, a FXU instruction that is dependent on an older LSU instruction must wait at dispatch until the LSU has accessed the Data Cache and is returning data. A Target Table is used to keep track of how architected results flow through the pipeline from the instruction dispatch through the architected facility Write Back (WB) stage. From this information, the Target Table can cause appropriate stall cycles for the dependent instructions to prevent dispatching of dependent instructions too early; e.g. before their operand data will be available. A target is defined as an architected facility that an instruction will write with its result. Typical targets are GPR (Fixed Point Register File), and FPR (Floating Point Register File). In this disclosure, the GPR target will be used as an example. The disclosure can be expanded to include other types of architected facilities.

The example Target Table in this disclosure is 32-entries deep; one entry per GPR destination register (RT) location as shown in Figure 1. Each entry has 4 unit bits to represent which execution unit is producing the result: FX0 represents FXU0 unit, FX1 represents FXU1 unit, LS0 represents LSU0 unit, and LS1 represents LSU1 unit.

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