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Bit Testing Bias Mechanism for Simultaneous Bidirectional Interfaces

IP.com Disclosure Number: IPCOM000030630D
Original Publication Date: 2004-Aug-20
Included in the Prior Art Database: 2004-Aug-20
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Abstract

This research disclosure describes a method and apparatus for bit testing bias on a simultaneous bidirectional interface which improves the testing and debug by enabling controlled isolation of bits within the bus.

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Bit Testing Bias Mechanism for Simultaneous Bidirectional Interfaces

Introduction

    High speed parallel interfaces such as the simultaneous bidirectional (SiBiDi) pose a challenge in testing link integrity due to its high speed nature as well as difficult, if not impossible probe point locations.

    Testing of these interfaces at the link level provide a bit/packet error rate. The bit bias mechanism described provides a test method and debug tool to isolate interface issues and weaknesses.

Current Method

    The current implementation of the SiBiDi interface and link macros include a ping test to check for link integrity through CRC checking and automatic packet generation.

    Paylod of the packet is obtained from a pseudo-random number generator. Bit-by-bit testing of this interface is very slow due to the lack of hardware mechanism to mask the data.

    Data from this test helps narrow the debug space to specific bit that limits the ability to have a low error rate

Proposed Method

    Proposed method would add a register that could mask bits of the data generator to emphasize a certain bit or bit combination improving testability.

    Hardware cost of this implementation is very low (16 bit register and 16 AND gates)

Faster, targeted testing at full speed provides quick debug direction.

Real Life / Issues

    Masking of the data does not mask the bits on the interface due to the necessity of packet headers and CRC.

    Masking, however, does introduce a bias in the error to the unmasked bits,...