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(RSS) Digitally controlled dual reference circuit

IP.com Disclosure Number: IPCOM000030631D
Original Publication Date: 2004-Aug-20
Included in the Prior Art Database: 2004-Aug-20
Document File: 6 page(s) / 57K

Publishing Venue

IBM

Abstract

This article describes a circuit designed to control the upper and lower reference voltages on an analog to digital converter used to read serially shifted analog light intensity data from a contact image scanner. The analog data provided by the scanner is provided as a 0 to 0.7 volt value on a 1.5 to 1.9 volt DC offset. The high variability of the DC offset from scanner to scanner requires that the upper and lower references used by the Analog to Digital converter be adjustable. In essence the upper reference must always be 0.7 volts above the lower reference. The lower reference must adjust from 1.5VDC to 1.9VDC to compensate for the changing scanner output reference.

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(RSS) Digitally controlled dual reference circuit

    While designing an application using a contact image scanning bar we found a problem where the DC offset of the analog output value from component to component was larger than the output range of the pixel light intensity. This requires that the scanner controller adapt the reference voltages of the analog to digital (A2D) converter to compensate. While the direct method of just adding a digital to analog converters (D2A) for each reference voltage is simpler, a better cost effective circuit was found. This circuit is not only cheaper; it is faster and utilizes less of the microcontroller's resources.

    The analog data provided by a digital scanner is provided as a 0 to 0.7 volt value on a 1.5 to 1.9 volt DC offset. The high variability of the DC offset requires that the Upper and Lower references used by the A2D converter be adjustable. Both references must be controlled so that they are always 0.7volts apart. The customary way to control the two reference voltages is to add two D2As, one controlling the upper reference and the other controlling the lower. This requires that both D2As be accurately controlled in tandem, maintaining a 0.7 volt difference with an error less than 0.05 volts. The D2As add cost to the solution as well as take up address space on the microcontroller's bus. There is also a problem maintaining the 0.7 volt difference within the error tolerance.

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Vcc

D/A Converter

S

V

B

B

V

GND

ENB

N bits of data

2

1

v

2

S

4

S C

2.2 VDC

D/A Converter

v

B

B

V

GND

V

ENB

3

S

1.5 VDC

Gnd

Gnd

Obvious Solution

Figure 1

The solution is a circuit that takes a single digital value and creates two voltages.

The first, lower reference voltage is controlled between 1.5 to 1.9 volts and the second, upper reference voltage, is always 0.7 volts greater than the lower reference voltage. All of this from a single 8 bit latch which is nearly a tenth the cost and uses only one bus address.

2

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Vcc

0

S

D0

D1

D2

Dn CLK

D0

D1

 D2Dn CLK

    Q D

Q

S

S

1

2

0

2 S

×

v

2

    Q D

Q

1

2 S

×

4 S

×

0

S C

S

    Q D

Q

4

4 S

×

v

.
.
.

1

2 S

n ×

1

    Q D

Q

0

1

2 S

n ×

3

S

Gnd

Example Circuit

Figure 2

    The example circuit is a generalization of the idea. The voltages v1 and v2 are the desired reference voltages. There are n bits of control. Each reference voltage is controlled by its associated resistor ladder. When all the bits in the latch bits are set, '1', both reference values are pulled to the high end of the range. When the latch bits are all cleared, '0', the reference values are pulled to the lower end of their range. Within the ladder network each resistor is progressively half as large as the last. The resistor associated with the least significant bit in the latch would have the smallest conductance, largest resistance, and the next resistor would have a value of conductance twice that of the next lowest. This is better understood when the...