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Split Read Hole/Write for Partial Writes in a Memory Controller

IP.com Disclosure Number: IPCOM000031122D
Original Publication Date: 2004-Sep-13
Included in the Prior Art Database: 2004-Sep-13
Document File: 6 page(s) / 76K

Publishing Venue

IBM

Abstract

A method for simplifying partial writes for a Memory Controller is described. The method makes use of a Coherency Unit for breaking apart the partial writes into cacheline type commands for the Memory Controller.

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Split Read Hole/Write for Partial Writes in a Memory Controller

In a computer system composed of one or more processors, an I/O subsystem, an optional scalability port (SP), and a DRAM memory subsystem, it is the job of the first chipset to glue all components together, passing commands between interfaces. The first chipset contains a memory interface controller subsystem that communicates with the underlying DRAM technology, implementing the necessary command to perform memory reads and writes. The first chipset also contains a processor bus interface, an I/O bus interface and an optional scalability port interface. There is also logic in the first chipset called the coherency unit to coordinate all interfaces and maintain correct system operation.

     In such a computer system, it is often necessary for the memory controller to write partial cacheline data out to memory. This can occur when the processor sources a partial (less than a cacheline size) write, or another interface such as I/O or a scalability port sources partial writes.

     To perform a partial write, the new partial write data must be merged with the existing data in the cacheline. If the memory technology supports byte enables on the write interface, this could be accomplished by one atomic write utilizing the write byte enables. However, not all memory technologies support the use of byte write enables, or don't support the granularity necessary to cover all partial write cases. Even in the direct connect case when the DRAM technology supports the necessary byte write enables, using a byte write enable would consume one extra pin for each byte width on the write data interface. Write partials are rarely a common enough operation that the extra pins on the package would be allocated for this.

     To overcome this memory technology limitation, previous generations of memory controllers have implemented partial writes as an atomic read-modify-write operation (RMW). The memory controller first issues a read, and discards the read data that overlaps with the write data. This is called a read hole operation. The read hole data is merged with the new write data, and then the entire new cacheline is written back to the underlying DRAM technology. This is a time-consuming operation, as it requires a read, waiting for the read precharge penalty to expire, followed by a write to the same bank. This operation has to occur atomically, and while it is executing, it blocks other accesses to that DRAM bank.

     Having the memory interface controller implement the write partial as an atomic RMW operation simplifies the logic for the coherency unit. When the coherency unit receives a write partial from the processor, I/O or SP interface, it can pass the write partial directly to the memory controller, and assume the write is ordered from that point on. However, as the memory controller portion of the first chipset increases in complexity, needing to support chipkill, scrub, mirroring, etc, impl...