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Utilizing Stalls to Correct Single Bit Errors in a Pipelined Cache Directory

IP.com Disclosure Number: IPCOM000031127D
Original Publication Date: 2004-Sep-13
Included in the Prior Art Database: 2004-Sep-13
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Abstract

Disclosed is a method for correcting single bit errors for a pipelined directory. The method utilizes stalls in order to reduce chip logic.

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Utilizing Stalls to Correct Single Bit Errors in a Pipelined Cache Directory

Typical SRAM/eDRAM cache directory designs use either parity or ECC to protect the directory contents. For a pipelined directory implementation utilizing ECC, there are three common hardware methods used to guarantee accurate cache directory information:
1) Add an additional pipeline stage or stages to correct the raw directory contents. Subsequent pipeline stages use the corrected data.
2) Calculate directory results bypassing the ECC correction logic (i.e., using uncorrected data). In parallel, compute the syndrome. If the syndrome reveals an ECC error, dynamically insert an additional pipeline stage that corrects the data and recomputes directory results.
3) Calculate directory results using the uncorrected data. In parallel, compute the syndrome. If the syndrome reveals an ECC error, retry the directory access, and force the subsequent access to use corrected data.

     Method (1) has an adverse affect on the latency required to compute directory results. In many of today's designs, directory results latency directory affects the overall memory latency. Since SRAM/eDRAM single-bit errors are a relatively infrequent event, unconditionally inserting unnecessary latency is not an optimal implementation.

     Method (2) has a negative impact on chip area due to the duplicate logic required to recompute directory results using the corrected data. In addition, subsequent transactions may observe increased latency until a pipeline bubble can be found.

     Method (3) essentially doubles the time required to calculate directory results for a transaction which encounters a single-bit error. Additional complexity may also be introduced due to the need to notify the directory results handler of the retried directory access.

     This invention capitalizes on SRAM/eDRAM designs (such as the IBM eDRAM) that hold their data outputs unt...