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Browse Prior Art Database

FinFET Compatible, 3 Dimensional Capacitor

IP.com Disclosure Number: IPCOM000031168D
Original Publication Date: 2004-Sep-15
Included in the Prior Art Database: 2004-Sep-15
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Abstract

An optimized physical layout is defined that limits capacitor series resistance while maximizing capacitive density for finFET technologies. Variations in length and width of the optimal capacitor will result in several possible implementations as the fin height, fin pitch, gate material, and silicon resistance change.

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FinFET Compatible, 3 Dimensional Capacitor

This invention describes a method to process and incorporate an on-chip capacitor using a 3-dimensional FET technology. The 3rd dimension (normal to the wafer surface) requires additional processing/layout considerations addressed in this disclosure. An optimized physical layout is defined that limits capacitor series resistance while maximizing capacitive density. Variations in length and width of the optimal capacitor will result in several possible implementations as the fin height, fin pitch, gate material, and silicon resistance change.

     The introduction of the third dimension (fin height) requires invention since the 2D approach for implanting dopant will no longer work (see Figure 3). The 2D approach which implants the dopant directly around the capacitor top plate area (nominally polysilicon) would not drive the bottom plate resistance nor allow for uniform concentration of the dopant. The dopant ions would not be able to penetrate the entire depth of the fin resulting in a greater concentration of dopant at the top of the fin than at the bottom. This, in turn, would make the device properties non-uniform, less predictable, and less effective as a capacitor. This invention describes an angled implant which will allow the entire fin (source/drain) to be uniformly doped with N+ dopant. This invention is based off the FET structures described in the references cited above. In order to achieve the electrical properties for a FET capacitor, the body of an Nfet device, which is normally diffused with N- dopant , is ultimately modified by the implantation of N+ dopants as in the source/drain regions of a traditional FET. Figures 1-2 show a migration from the traditional capacitor to one with the nominal, lightly doped body regime. The Nfet model is used for a capacitor because Nfet effective resistance (particularly of the body) is typically lower than a Pfet due to higher electron mobility.

     The...