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Pre-Determined Logic State for CMOS Circuit at Power-On

IP.com Disclosure Number: IPCOM000031169D
Original Publication Date: 2004-Sep-15
Included in the Prior Art Database: 2004-Sep-15
Document File: 4 page(s) / 75K

Publishing Venue

IBM

Abstract

This invention will allow the memory elements to have a predefined logic state as the chip power-on without additional circuitry and control logic. This invention will take less chip area, lower power, and simplify the chip design over traditional methods.

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Pre-Determined Logic State for CMOS Circuit at Power -On

Computer chips contain many memory elements. The logic state of most of these memory elements do not require to be at a known state as the power on condition. However some percentage of these memories are required to have a known state at power on.

     Traditionally this was accomplished by designing the memory elements with extra circuitry to set/reset their states to a desirable logic value, shown in Figure 1. This method required additional circuits and control logic to drive the memory. This adds power and complexity to the chip design.

     This invention will allow the memory elements to have a predefined logic state as the chip power on without additional circuitry and control logic. This invention will take less chip area, lower power, and simplify the chip design over the traditional method.

     The schematic of this invention is shown in Figure 2. Transistors N1-N5, and P1-P2 are lower Vt types compared to the other transistors in Figure 2. The higher DC leakage current of the lower Vt devices will allow the memory circuit in Figure 2 to come up in the predetermined state at the power on condition without the need of additional devices and control logic. Figure 3 shows the Spice simulation of the circuit in Figure 2. The combination of leakage currents generated by lower Vt PFET (P1) pulls node L1_TP to VDD, and the lower Vt NFETs (N1-N3) ensures the circuit will come up with the proper logic state at power on...