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The method of building of full-duplex serial synchronous communication means based on special cycle buffer.

IP.com Disclosure Number: IPCOM000031189D
Original Publication Date: 2004-Sep-16
Included in the Prior Art Database: 2004-Sep-16
Document File: 2 page(s) / 87K

Publishing Venue

Motorola

Related People

Alexander Semjonov: AUTHOR

Abstract

This paper is devoted to improvement of serial synchronous device and driver architecture. The serial synchronous devices are full duplex serial ports, which are used to communicate between microcontrollers and peripheral devices. Such communication is typically established to transfer data on high sampling rate, thus serial synchronous interface is a bottleneck of microcontrollers performance. The proposed architecture reduces interface overhead and optimize implementation.

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Document Title: The method of building of full-duplex serial synchronous communication means based on special cycle buffer.

Authors’ Name(s): Alexander Semjonov

   

Abstract 

This paper is devoted to improvement of serial synchronous device and driver architecture.

The serial synchronous devices are full duplex serial ports, which are used to communicate between microcontrollers and peripheral devices. Such communication is typically established to transfer data on high sampling rate, thus serial synchronous interface is a bottleneck of microcontrollers performance. The proposed architecture reduces interface overhead and optimize implementation.    . 

Problem

The standard decision for most of software drivers and hardware devices is to have two dedicated FIFO (First Input First Output) buffers separately for reception and transmission.

The FIFO decision reduces requirements for processor interrupt latency for lower priority activities. All exiting decisions for software and hardware serial synchronous interfaces can be reduced to the following scheme(see Fig. 2).

The FIFO buffer break down structure is N elements to save data samples and two pointers for "get" and "put" operations. (There are another versions to call these pointers as  "read/write" or "begin/end"). Buffer pointer is a handle to provide "get" or "put" procedures with buffer elements. "Interface logic" puts data samples to the transmission FIFO buffer for further transmission and gets received data samples from the receive FIFO buffer. "Shift register(s) logic" gets data sample for transmission and puts just received data sample into FIFO buffer. "Interface logic" is an asynchronous sub-system because the user application can "get" or "put" data samples independently any time.  The "Shift register(s) logic" is a synchronous receiver/transmitter sub-device, so "get" or "put" have to be done concurrently (parallel "get" or "put" operation have to be done for one time quantum).          

The solution of two hardware FIFO buffers is complex and expensive. When the receive FIFO buffer is full then the transmission FIFO buffer is empty, therefore the number of buffer elements is redundant. A robust software driver should perform error conditions of both FIFO hardware buffers. There is no hardware synchronization between both buffers; thus it is a software driver extra overhead.

Solution

The proposed decision is...