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Scaled Size/Frequency Multiphase Converter

IP.com Disclosure Number: IPCOM000031287D
Published in the IP.com Journal: Volume 4 Issue 10 (2004-10-25)
Included in the Prior Art Database: 2004-Oct-25
Document File: 4 page(s) / 471K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Usually, to increase the efficiency of the power supply for CPUs, several different modulation techniques are employed. A very common procedure is to use a fixed frequency PWM (Pulse Width Modulation) technique for load currents above a certain threshold, while the system automatically switches to a PFM (Pulse Frequency Modulation) technique below that value in order to minimize the switching losses at low currents. Another more recent method is to use an auxiliary phase, an alternative conductor with smaller dimensions, which is activated when the load current falls below a prefixed value. Likewise, this reduces the switching losses and thereby enhances the efficiency for low currents. In the following, this approach is extended by using several phases. The size of the power devices and the frequency of these phases are scaled with respect to a reference phase. For the latter, the phase with the smallest components and the lowest frequency can be used. This 'smallest' phase is always running. As soon as the output current exceeds the first threshold, the second phase is activated. The output current is then split, so that the reference phase now carries its maximum allowed current (I1max), while the second phase carries the rest. As the output current increases, the other phases are activated in turn. Thereby, the switching losses increase with the size of the power devices, while the conduction losses decrease. Figure 1 shows an example of this mechanism with three phases. Here the values for the different thresholds are I1max = 1/6*Imax, I2max = 1/3*Imax and I3max = 1/2*Imax. The overall load is the sum of the currents in each phase, and therefore the maximum load equals (1/6 + 1/3 + 1/2)*Imax = Imax.

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Scaled Size/Frequency Multiphase Converter

Idea: Giuseppe Bernacchia; IT-Padova; Riccardo Pittassi, IT-Padova

Usually, to increase the efficiency of the power supply for CPUs, several different modulation techniques are employed. A very common procedure is to use a fixed frequency PWM (Pulse Width Modulation) technique for load currents above a certain threshold, while the system automatically switches to a PFM (Pulse Frequency Modulation) technique below that value in order to minimize the switching losses at low currents. Another more recent method is to use an auxiliary phase, an alternative conductor with smaller dimensions, which is activated when the load current falls below a prefixed value. Likewise, this reduces the switching losses and thereby enhances the efficiency for low currents.

In the following, this approach is extended by using several phases. The size of the power devices and the frequency of these phases are scaled with respect to a reference phase. For the latter, the phase with the smallest components and the lowest frequency can be used. This 'smallest' phase is always running. As soon as the output current exceeds the first threshold, the second phase is activated. The output current is then split, so that the reference phase now carries its maximum allowed current (I1max), while the second phase carries the rest. As the output current increases, the other phases are activated in turn. Thereby, the switching losses increase with the size of the power devices, while the conduction losses decrease. Figure 1 shows an example of this mechanism with three phases. Here the values for the different thresholds are I1max = 1/6*Imax, I2max = 1/3*Imax and I3max = 1/2*Imax. The overall load is the sum of the currents in each phase, and therefore the maximum load equals (1/6 + 1/3 + 1/2)*Imax = Imax.

The proposed solution allows for the converter to always operate in the PWM mode without requiring complicated circuitries for activating the different phases. For example in a current mode controller, a sense current ISi of each phase can be compared to the output of an error amplifier. Figure 2 shows a very simple implementation of this decision circuitry. The error amplifier gain is designed in such a way that its maximum output current corresponds to the maximum current allowed for the minimum phase, I1max. Therefore, the loop for this phase consists of the sense current and of a 1:1 mirror current from the error amplifier. If N2 and N3 are the ratios of the component dimensions of Phase 2 and Phase 3, then the maximum output currents for these p...