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A Method for doing Memory Error Injection using a CPLD to get around Constraints

IP.com Disclosure Number: IPCOM000031368D
Original Publication Date: 2004-Sep-22
Included in the Prior Art Database: 2004-Sep-22
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Abstract

Memory Error Injection using a CPLD to target specific address ranges

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A Method for doing Memory Error Injection using a CPLD to get around Constraints

    For our testing purposes, we need to bug the memory data bus by creating single bit and double bit errors. Our present solution generates these errors throughout the whole DIMM, which presents the problem that we cannot bug certain banks of memory because it contains the BIOS/DIAGS/USB code (usually lower and upper banks) which only occupies a few KB of space. Testing is therefore limited because we are not able to check how those banks behave (even if they contain 4 GB of mem). The problem will get worse with systems based on the Lindenhurst chipset because the MCH here will group all memory into one bank if all DIMMs are of the same technology. This would mean that we won't be able to inject errors anywhere when we have that configuration, so our testing can not be performed to its fullest.

    The solution is to use a CPLD to inject an error at a given address or range of addresses in memory at the time that memory space is addressed.

    The plan is to use the CPLD to monitor the address coming from the memory controller hub and compare it to the address given by the user. If there is a correct match, then turn off a bus switch (or NFET transistor) and make the output from one of the data bits Hi-Z (the preferred method is to invert the bit). Since we are only injecting the error when a given address is present, we can set it to bug a memory location outside the range of the code, theref...