Browse Prior Art Database

Flexible Plug Configurations for Performance Address Translations

IP.com Disclosure Number: IPCOM000031556D
Original Publication Date: 2004-Sep-29
Included in the Prior Art Database: 2004-Sep-29
Document File: 5 page(s) / 70K

Publishing Venue

IBM

Abstract

A method for translating memory addresses that support multiple plug configurations with a performance address map is disclosed.

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This is the abbreviated version, containing approximately 22% of the total text.

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Flexible Plug Configurations for Performance Address Translations

Address normalization and translation are required in large memory subsystems to translate real addresses (i.e., system addresses) to physical addresses (i.e., DRAM addresses). To reduce latency for higher performance, it is desirable to determine the Chip Select Group (i.e., Memory Rank), DRAM Internal Bank Select, and the DRAM Row Address as fast as possible to detect potential collisions against commands already in progress and, if no collisions, begin the Row Activate to the DRAMs immediately. To achieve this, performance address maps are architected to minimize the amount of logic required to obtain these critical portions of the physical address. Use of such performance address maps have some limitations/restrictions.

     To better understand the limitations/restrictions associated with a performance address map, a brief discussion of a general address map is warranted. A general address map must be able to account for mixed DRAM technologies physically plugged in any combination of memory ports and any combination of ranks within each memory port. The physical plug configuration must be logically re-arranged to configure the larger memory technologies at the bottom of the memory space to avoid gaps in memory. Because of this, it is implicit that the rank encode bits are the most significant bits of the address. A system address must first be normalized to account for any memory base address offset in a multi-node system, for memory "holes" which allow reclaiming DRAM address regions that would not be usable because that space is allocated for MMIO or perhaps to account for a memory cache which is not visible system address space. Once normalized to a physical address, the memory port, rank (or Chip Select) within the port, and the DRAM address (Row, Column, Internal Bank Select) within the rank are determined by additions, subtractions, and comparisons. When supporting every possible configuration as well as specific functions such as different interleaving modes or memory mirroring, several clock cycles are needed to perform the normalization and translation before the access can be initiated to DRAM.

     As referred to above, performance address maps are architected to minimize the amount of logic required to obtain critical portions of the address and are only supported with specific memory configurations. Previous chipsets require that ranks 0 to n are populated with homogeneous DRAM technology. The Rank then becomes a straight decode from a select field within the system address, eliminating the need for comparisons against individual rank base address offsets. Additionally, for cases where the number of ranks configured is a power of 2, the rank encode bits may be mapped to lower order system address bits. These bits would be required to be below the smallest granularity of the memory base offset, memory hole, memory cache, etc thus eliminating the need to perf...