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SINGLE STEPPING CO-PROCESSOR OPERATIONS FOR DESCRIPTOR DEBUGGING

IP.com Disclosure Number: IPCOM000031769D
Original Publication Date: 2004-Oct-08
Included in the Prior Art Database: 2004-Oct-08
Document File: 5 page(s) / 131K

Publishing Venue

Motorola

Related People

Tom Tkacik: AUTHOR [+2]

Abstract

We designed an encryption co-processor with a DMA that reads programmable linked-list style of descriptors chains to execute a series of cryptographic functions. It became apparent early in the design phase that with little observability into the hardware's inner workings, locating and fixing errors in the descriptor chain would be difficult. Each chain is a series of descriptors and each descriptor itself usually involves a set of complex tasks that due to various internal processing rates and factors may execute in a sequence that is not easy to predict. To make debugging easier we developed a mode for stepping through the execution of the descriptor chain. Each step performs a hardware-generated operation, often a bus transaction such as fetching a link or writing data, or sometimes waiting for a buffer to become available. After each operation the co-processor is stalled and we can see what the hardware is "thinking next" in a status register. The next operation is made visible in a set of debug registers when the debug mode is entered. It is based upon the current descriptor, controller, accelerator, and buffer states. When a software driver was being developed for this module, this fine-grained control and observability over the descriptor chain execution helped answer many questions quickly and undoubtably sped up the development time.

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single Stepping co-processor Operations for descriptor DebugGINg

by Tom Tkacik and

Lawrence

Case

October 6, 2004


Abstract

We designed an encryption co-processor with a DMA that reads programmable linked-list style of descriptors chains to execute a series of cryptographic functions. It became apparent early in the design phase that with little observability into the hardware's inner workings, locating and fixing errors in the descriptor chain would be difficult. Each chain is a series of descriptors and each descriptor itself usually involves a set of complex tasks that due to various internal processing rates and factors may execute in a sequence that is not easy to predict.

To make debugging easier we developed a mode for stepping through the execution of the descriptor chain. Each step performs a hardware-generated operation, often a bus transaction such as fetching a link or writing data, or sometimes waiting for a buffer to become available. After each operation the co-processor is stalled and we can see what the hardware is “thinking next” in a status register. The next operation is made visible in a set of debug registers when the debug mode is entered. It is based upon the current descriptor, controller, accelerator, and buffer states.

When a software driver was being developed for this module, this fine-grained control and observability over the descriptor chain execution helped answer many questions quickly and undoubtably sped up the development time.

Introduction

The cryptographic co-processor can be used on cellphone baseband processors or wireless PDAs. It implements common block encryption, public key, and hashing algorithms, and includes a random number generator. It has a slave interface for the host to write configuration and command information, and to read status information. It has a descriptor-based controller with a DMA to reduce the burden on the host of moving data to and from memory.

Development of the descriptor chains is the key to using the co-processor. These chains are the sets of instructions that determine the functions, the modes, the data (and keys), and the order in which everything is executed. To process a chain, software writes the address of the first descriptor in the chain to the co-processor. The co-processor then runs the sequence to completion and generates an interrupt when done. The sequence of descriptors can be as long as needed and no interaction between the co-processor and host is necessary while the chain is executing.

Allowing software-programmable descriptor chains increases the adaptability of the cryptographic accelerators to various protocols but it also increases the opportunity for mismanagement of the co-processor controller as these descriptor chains can become quite complex. Furthermore, by allowing the sequence to run to completion in hardware without interaction, although increasing performance, can make debugging the long sequence of steps difficult. To assist in the develo...