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Ethernet PHY Management Broadcast-Write-As-0 Protocol

IP.com Disclosure Number: IPCOM000032244D
Publication Date: 2004-Oct-26
Document File: 2 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a technology-independent digital logic that allows all ports in a product to respond with register data when a particular programmed address (PA) is accessed. Benefits include improving the initialization speed of the ports in a multi-port device.

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Ethernet PHY Management Broadcast-Write-As-0 Protocol

Disclosed is a method for a technology-independent digital logic that allows all ports in a product to respond with register data when a particular programmed address (PA) is accessed. Benefits include improving the initialization speed of the ports in a multi-port device.

Background

Currently, the standard interface provides register access (i.e. read and write) for up to 32 ports on a single management bus. This interface consists of an “MDC” (i.e. bus clock) and an “MDIO” (i.e. bidirectional serial data signal). All devices on the bus have a programmed address (PA), which distinguishes the devices from each other.

The current register access operation passes controlled information to the MDIO signal, followed by the register data, which is generated by a specific port during read operations and by the management entity during write operations (see Figures 1 and 2). The figures show the MDIO signal being split into an incoming “MDI” signal, an outgoing “MDO” signal, and an output-enable “MDOEN” signal). Each access is exactly 64 bits in duration; the 32 bits of preamble are not shown in the figures.

General Description

The disclosed method enables all ports in the product to update a register when a particular PA is accessed. This implementation exists between the management pins of the device and the management logic of all ports in the device.

A write operation (see Figure 2) causes a single port t...