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Smart Power Integrated Circuit Design Architecture with Enhanced High-Side Breakdown Voltage

IP.com Disclosure Number: IPCOM000032246D
Original Publication Date: 2004-Oct-26
Included in the Prior Art Database: 2004-Oct-26
Document File: 5 page(s) / 2M

Publishing Venue

Motorola

Related People

Vishnu Khemka: AUTHOR [+4]

Abstract

In this disclosure we propose a novel and unique process design architecture directly applicable to smart power integrated circuits, for achieving very high high-side breakdown voltage without enhancing process complexity. The technique is specially suited to smart power platforms where high-voltage devices are integrated with low and medium voltage devices using deep trench based isolation.

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Smart Power Integrated Circuit Design Architecture with Enhanced High-Side Breakdown Voltage

Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu and Amitava Bose

Abstract:          In this disclosure we propose a novel and unique process design architecture directly applicable to smart power integrated circuits, for achieving very high high-side breakdown voltage without enhancing process complexity. The technique is specially suited to smart power platforms where high-voltage devices are integrated with low and medium voltage devices using deep trench based isolation.

In a typical deep sub-micron smart power technology with trench based isolation and heavily doped n-type buried layer on P++ substrate the high-side breakdown voltage that can be realized is limited not only due to the lightly doped epitaxial thickness available between the n-type buried layer and the P++ substrate but also due to the electric field crowding at the corner where buried layer (lying under the whole device) intersects the deep trench isolation around the periphery of the device. High-side breakdown voltage refers to the voltage that can be sustained between the device isolating n-type buried layer and the heavily doped p-type substrate. A simple increase in the epitaxial layer thickness does not produce an increase in the breakdown voltage. In addition an increase in epitaxial layer thickness is not always desirable as it can lead to several unwanted minority carrier substrate injection scenario. Availability of a thicker lightly doped region can provide a relatively high life-time path for minority carriers which can then travel far into the integrated circuits thus disturbing normal operation. Fig.1 illustrates the high electric field at the buried layer to deep trench intersection point with the help of two-dimensional simulations. It is desirable to first achieve a true one-dimensional breakdown voltage determined by the buried layer to substrate by eliminating the electric field crowding.

The proposed idea relies on the fact that if the electric field crowding is appreciable in a two-dimensional corner as shown in Fig.1, it must be significantly worse in the third dimension (looking from the top). We propose two alternate schemes of eliminating this intense electric field crowding. In the first scheme the corners of the peripheral trench is rounded with appropriate radius of curvature so as to alleviate the electric field crowding. In the layout, each device that requires high-voltage capability will have its trench corner rounded with appropriately designed radius of curvature so as to obey design rules.

 In addition this technique requires a slight increase in epitaxial thickness compared to the standard. Fig.2 shows the top-view of two adjacent devices in a power IC requiring high high-side capability.

In the second scheme, epitax...