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Method for memory synchronization in SMP systems

IP.com Disclosure Number: IPCOM000032358D
Publication Date: 2004-Nov-02
Document File: 6 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for memory synchronization in symmetric multiprocessor (SMP) systems. Benefits include improved functionality and improved performance.

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Method for memory synchronization in SMP systems

Disclosed is a method for memory synchronization in symmetric multiprocessor (SMP) systems. Benefits include improved functionality and improved performance.

Background

              Desktop application markets are characterized by a requirement for low to high-end scalable performance platforms, and SMP plays a pivotal role in these markets. However, as demonstrated by the performance measurement analysis indicates the benefits of SMP are marginal and in many cases nonexistent. The main reason is that these applications are characterized as input/output (I/O) and memory bound with large system overhead and not much CPU intensive processing. Therefore, the use of front-side bus (FSB) locking mechanisms surface as an important performance factor in embedded and input/output (I/O) centric applications.

              Instructions that use the LOCK prefix are commonly called atomic instructions. Their purpose is to prevent other processors in the system to access the shared memory area to guarantee exclusive use of the resource, and thus to avoid memory synchronization issues and “race” conditions. However, there are various side effects of using this mechanism that may degrade overall system performance.

              Multiprocessor systems use a bus locking mechanism to prevent multiple processors from using or modifying a shared system resource simultaneously. A processor LOCK signal is asserted using a LOCK instruction accompanied by another instruction.

              By locking the front side bus, other processors in the system cannot access any system resource, even if it is not shared memory, while the LOCK signal is asserted. They can only continue to function if all the code and data they require has been copied into their local cache. For example, in a dual-processor (DP) system (see Figure 1), if processor 1 locks the bus, it prevents processor 2 from getting access to any system resource, even if processor 2 is not attempting to access the same resource as processor 1 (see Figure 2). Processor 2 stalls until the bus is released. An example of the operation flow is as follows:

1.           Processor 1 locks the front-side bus (FSB) to access a system memory variable.

2.           Processor 2 attempts to access another area of system memory to read information from a peripheral device and stalls when the bus is locked.

3.           Processor 1 completes its system memory transaction.

4.           Processor 2 can continue accessing system memory.

              Due to the out-of-order execution engine, the processor pipeline is emptied to ensure that none of the instructions in the processor pipeline try to reference the shared resource. Additionally, all instructions must be retired and written back to memory before the lock instruction is executed. Performance penalties occur due to pipeline serialization.

              The use of the LOCK freezes all processor resources within a physical package, stopping the execution o...