Browse Prior Art Database

Method for SDRAM clock-enable control circuitry to nonstandard SDRAM during power-down mode

IP.com Disclosure Number: IPCOM000032359D
Publication Date: 2004-Nov-02
Document File: 4 page(s) / 43K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for synchronous dynamic random access memory (SDRAM) clock-enable control circuitry to nonstandard SDRAM during power-down mode. Benefits include improved functionality and improved performance.

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Method for SDRAM clock-enable control circuitry to nonstandard SDRAM during power-down mode

Disclosed is a method for synchronous dynamic random access memory (SDRAM) clock-enable control circuitry to nonstandard SDRAM during power-down mode. Benefits include improved functionality and improved performance.

General description

              The disclosed method is an interface to nonstandard SDRAM that requires no POWER DOWN command before entering power-down mode. This circuitry enables interfacing to both standard SDRAM and nonstandard SDRAM by the use of the ENABLE input signal.

Advantages

              Some implementations of the disclosed structure and method provide one or more of the following advantages:

•             Improved functionality due to providing an interface to standard and nonstandard SDRAM by the use of the ENABLE input signal

•             Improved performance due to requiring no POWER DOWN command before entering power-down mode

Detailed description

              The disclosed method is a circuit that enables a memory controller to interface to nonstandard SDRAM memory that cannot accept a POWER DOWN command before entering power-down mode. The POWER DOWN command is defined when the SDRAM Chip Select (nCS) is high and SDRAM clock enable (CKE) is low at the rising edge of SDRAM clock (CLK, see Figure 1).

              The circuitry changes the POWER DOWN command into a no operation (NOP) command before sending the command to the nonstandard SDRAM. Holding the CKE signal high during the normal POWER DOWN command cycle, rather than letting it go low, changes the POWER DOWN command into a NOP command (see Figure 2).

              Cycle 3 would typically be the POWER DOWN command sent to a standard SDRAM (see Figure 3). However, the circuitry holds the CKE signal high to the SDRAM by one clock, changing the POWER DOWN command into a NOP command. Cycle 5 is a typical POWER DOWN EXIT command and the circuit does not interfere with this command and allows this command to transmit uninhibited to the nonstandard SDRAM. For the special case when the POWER DOWN command is immediately followed by a POWER DOWN EXIT command, both of these commands are changed into NOP commands, which has no effect on the nonstandard SDRAM.

              The disclosed method does not interfere with any other SDRAM command, including POW...