Browse Prior Art Database

Method for 0-mV circuitry for statistical failure analysis on the silicon of a dynamic SAs used in small signal arrays

IP.com Disclosure Number: IPCOM000032360D
Publication Date: 2004-Nov-02
Document File: 5 page(s) / 40K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for 0-mV circuitry for statistical failure analysis on the silicon of a dynamic sense-amplifiers (SAs) used in small signal arrays (SSAs). Benefits include improved functionality and improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 47% of the total text.

Method for 0-mV circuitry for statistical failure analysis on the silicon of a dynamic SAs used in small signal arrays

Disclosed is a method for 0-mV circuitry for statistical failure analysis on the silicon of a  dynamic sense-amplifiers (SAs) used in small signal arrays (SSAs). Benefits include improved functionality and improved performance.

Background

      A lower SA differential requirement helps make the arrays less critical in timing. Conventional circuitry is limited in its capability to analyze the failure of a dynamic SA and to indicate how close a SA design is to failure. Consequently, designers must use theoretical analysis of the voltage differential required at the SA sense nodes. Silicon data cannot be used. This issue is becoming increasingly critical. The SA differential requirement, based on theoretical analysis, is not scaling from one process generation to another. Silicon-based data is required to make the SA requirement scale from one process to its subsequent process. The results from 0-mv analysis can be used to reduce the SA differential requirement in subsequent versions of the product or future product and can make SSA less timing critical.

              One of the areas of interest for design, debug, and product engineers is to study the function of dynamic SAs on silicon. The engineers need to understand if the voltage differential developed at the sense nodes of the SA is adequate. Additionally, the variance of the nominal or theoretically-calculated differential requirement from the critical value that results in the actual (sensing) failure must be understood.

              The initial estimation of the SA differential requirement is conventionally based on the mismatch numbers from the process file and theoretical analysis. Generally, theoretical analysis is simulated under pessimistic assumptions. The variance of the theoretical calculation from the real data on silicon is required.

      One conventional solution is to use software-controlled timing (SCT) for embedded arrays. SCT is fully programmed to enable the earliest sensing of the SA. By introducing a software programmable delay element into the array, the timing of various array controls can be altered to ensure a functional, reliable circuit (see Figure 1). However, even at the full programming, the SA is not enabled early enough to make it fail. SCT does not have enough range to cause a reasonable failure and does not provide an adequate solution.

              The input/output (I/O) control circuitry coupled to the embedded memory array requires a programmable delay circuitry to alter the timing of the I/O signal, namely, sense amplifier enable (SAEN). The programmability is provided using the SCT array. Depending on the number of cells programmed in SCT array, the time at which the SAEN arrives at the embedded memory can be manipulated.

              The programming of the SCT column creates a delay curve (see Figure 2). As more cells are programm...