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Dual Port SPI with Hybrid Multiplexer / Test-and-Set Arbitration

IP.com Disclosure Number: IPCOM000032368D
Original Publication Date: 2004-Nov-03
Included in the Prior Art Database: 2004-Nov-03
Document File: 5 page(s) / 126K

Publishing Venue

Motorola

Related People

Carl Wojewoda: AUTHOR [+3]

Abstract

A shareable resource is described that has two communication ports; these two ports give access to control bits. Optimization of performace versus area leads to a hybrid approach where some of these are controled through a high performance Multiplexer means and other bits are controlled via a lower performance but more flexible test-and-set means.

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Dual Port SPI with Hybrid Multiplexer / Test-and-Set Arbitration

AUTHORS

Carl Wojewoda
Richard Unetich
Cor Voorwinden

ABSTRACT

A shareable resource is described that has two communication ports; these two ports give access to control bits. Optimization of performace versus area leads to a hybrid approach where some of these are controled through a high performance Multiplexer means and other bits are controlled via a lower performance but more flexible test-and-set means.

BACKGROUND

In many applications, such as advanced mobile phones, two processors are used. These processors will need to share certain resources. This presents a problem in sharing those resources safely and efficiently.

Certainly, one approach be to have one of the processors could control that resource directly, and the other processor could act as a relay and thereby allow the other processor to control that shared resource. However, that is not very efficient because in many applications, the two processors are allowed to go to low-power "sleep" modes independently. This poses a severe message latency limit on the processor that acts as the message relay.

The other major stategy is to have two communication ports on the shared resource. This removes the message latency issue, but now raises the equally important issue of assuring that the two processors do not interfere with those shared resources. Consider the case where the shared resource is controlled through a set of registers that both processors have write access to. It is very likely that there will be a time that both processors would try to write to a given register, Register A, at the same time and the resulting contents could be garbled data that neither processor intended to write. (See Figure 1.)

One safe approach would be to divide the set of registers so that, for example, Processor A can only write to registers A0-An, and Processor B could only write to registers B0-Bn. (This could, of course be stated to say that both processors could write to all registers, but that for each register, the bits are uniquely allocated with a set of bit that only Processor A could affect, and a set of bits that only Processor B could affect.) This is certainly safe and efficient, but it is not very flexible. Once the shared resource is made, there is no means to dynamically re-allocate the registers or bits. Therefore if a new allocation would be needed, a new resource would have to be re-manufactured - which is, of course expensive in terms of both time and money.

One solution known in the prior art is to to have a control means to allow the bits in the registers dynamically reallocated. Ballantyne et al describe a system where one processor has sole access to a set of configuration registers, both registers write to a set of intermidiate registers, and the shared is controlled by a function of the intermediate registers determined by the configuration registers. For example, if bit 4 of register 7 enables a regulator and...