Power On Self Test Boot Loader: Same Image Runs Different Depending on Load Location
Original Publication Date: 2004-Nov-03
Included in the Prior Art Database: 2004-Nov-03
The invention is to make the host adapter POST (Power On Self Test) boot loader and the POST code work so that the same POST image runs different depending on load location.
Power On Self Test Boot Loader : Same Image Runs Different Depending on Load Location
Disclosed is a method to make a POST (Power On Self Test) boot loader and the POST code work so that the same POST image runs different depending on load location.
On an adapter, the time it takes to run the Power On Self Test (POST) is important because the time affects the amount of time for the machine to IML or config during normal customer operation. One embodiment of a host adapter has two memory types, SRAM, which is faster, and DDR memory. The POST would run quicker running out of the SRAM. However, some of the POST tests were required to execute out of the DDR memory because the tests tested the IBATs, Instruction Block Address Translation, for stuck bits. To execute the code out of the SRAM instead of the DDR memory required the IBATs to have useful values instead of patterns for testing for stuck bits. So, the POST tests were divided into certain tests that would be executed from the SRAM and certain tests that would be executed out of the slower DDR memory. The POST code resides in the flash and then gets copied from the flash to memory, where the code executes. We did not have enough flash space on the adapter to have one flash image for the SRAM POST, meaning it runs out of the SRAM, and one flash image for the DDR POST, meaning it runs out of the DDR memory. However, since the addresses for the SRAM and the DDR memory were different, code was needed that could run out of either addresses that are SRAM or DDR memory. The code the compiler generated did not allow the code to be executed out of both memory addresses.
The invention is to have a method of combining 2 separate Executable Images (SRAM POST and DDR POST) into 1 executable Image (POST) that would execute no matter where the Executable Image (POST) was loaded, be it SRAM at address 0x20000000 or DDR at address 0x00000000. The mechanics of setting up the embedded system's physical and logical address is left up to the POST boot loader code.
The microprocessor has IBATs, Instruction Block Address Translation, which can translate an effective address to a phys...