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Single-Ended Open-Loop Level Shifter Circuit

IP.com Disclosure Number: IPCOM000032709D
Original Publication Date: 2004-Nov-10
Included in the Prior Art Database: 2004-Nov-10
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Abstract

The current invention relies on a pull-up or pull-down resistor in the first stage of a level shifter circuit. The second, buffer stage ensures rail-to-rail output with adequate power to drive a load.

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Single-Ended Open-Loop Level Shifter Circuit

Disclosed is a simple level shifter circuit that is single-ended and doesn't rely on cross-coupling or feedback of any sort, as is often the case with current implementations. This open loop characteristic makes it more flexible in design and avoids additional buffer stages typically used to ensure a known load on any feedback node. Its overall simplicity and small device count also translate to a smaller propagation delay. This circuit is primarily intended for relatively small level shifts, such as 0.8V supply to 1.0V supply or vice-versa.

    An input signal from one power domain (vdd1) is applied to the circuit in Fig. 1. This circuit is supplied by another power source with different voltage (vdd2). Within the circuit, a CMOS-like inverter input stage is implemented with a pull-up or pull-down resistor in place of one of the FETs. Since the input level is somewhat unknown, the signal just needs to turn the input FET on enough to fight the resistor and pull the intermediate node (net1) toward power/gnd. Because of the analog nature of this input stage, a voltage drop develops across the resistor when the input FET is turned on. To address this, the intermediate node (net1) is fed through a traditional CMOS inverter output stage to ensure the final output is rail-to-rail. Note that the design using a pull-up resistor is best suited for shifting the input level up from a lower power supply to a higher one (vdd1 < vdd2). A design with the resistor in the pull-down portion of the input stage is best used for shifting the input signal down to a lower level (vdd1 > vdd2).

    Although a resistance is needed on the input stage, if the semiconductor technology used doesn't support resistors per se, a FET can be used instead. With the FET implementation, the gate of the "resistor" FET is tied to power (NFET) or ground (PFET). For additional flexibility, such as...