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Disabled Interrupt Processing Model with Deferred Execution

IP.com Disclosure Number: IPCOM000033027D
Original Publication Date: 2004-Nov-22
Included in the Prior Art Database: 2004-Nov-22
Document File: 2 page(s) / 64K

Publishing Venue



Platforms such as Power use a priority interrupt model that allows the operating system (AIX) to disable interrupts at or below a given priority while still permitting interrupts above that given priority. Within this model, the operating system can defer certain activities such as specific classes of I/O completion processing, until the thread's interrupt priority is set to some lower interrupt priority. This article describes a method to model this hardware/operating system behavior in the absence of the actual hardware supported capabilities, specifically to provide the correct I/O completion semantics expected by AIX device drivers.

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Disabled Interrupt Processing Model with Deferred Execution


The reference platform that first utilized this approach is the z/Series Portable I/O support; refered to here as "the Container".

Each thread operating in the Container has a thread extention associated with it and containing a field that is used to identify the thread's current interrupt priority, as understood by AIX on the p/Series hardware. This allows the system to identify the thread's current interrupt priority. When Container services are called by a device driver in order to change the thread's interrupt priority, the new priority is saved in the thread extention.

The Container model uses the interrupt priority saved in the thread extention to determine whether or not to defer execution of I/O completion routines. If the thread's current interrupt priority is at or higher than that of a specified interrupt priority (INTIODONE), the I/O completion processing is deferred . At the time when the thread's interrupt priority is returned to a priority below that of the specified interrupt priority (INTIODONE), the deferred I/O completion requests from that thread are all processed.

The advantage is that this model allows for simulating the Power/AIX interrupt priority and deferred I/O completion semantic while still efficiently and effectively provide for the scheduling of defered I/O completion processing, without the need to introduce foreign interrupt semantics to zSeries HW or OSes.

In More Detail...

The Container's thread extention associated with each thread contains two data elements:

Current interrupt priority - A value representing the current simulated interrupt


priority from Power/AIX. The symbolics for the interrupt priorities pertinent to this discussion can be limited to INTBASE (lower priority) and INTIODONE...