Browse Prior Art Database

Fifo Cascading

IP.com Disclosure Number: IPCOM000033037D
Original Publication Date: 2004-Nov-22
Included in the Prior Art Database: 2004-Nov-22
Document File: 1 page(s) / 32K

Publishing Venue

IBM

Abstract

The invention described here after is a method of using the same hardware for both multiple small fifos and unique big fifo.

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Fifo Cascading

Description of the fifo cascading

There are some applications that need to pass information from one clock domain to another one. To avoid having metastability problems or loose any data in these process, a fifo is used. In some cases, several fifos are working in parallel to deal with multiple flow of data. And in some particular cases, there is a need to have the possibility of having either several small fifos in parrallel or having one unique fifo with a bigger size. For instance, in video application, the same device can have to deal with either a Y Cr Cb flow of data to be stored into 3 fifos , or a RGB flow of data to be stored into 1 fifo.

The invention described here after, is a method of using the same hardware for both multiple small fifos and unique big fifo.

The usual method to do such thing is to have one set of multiple hardware to manage the fifo pointers for the multiple fifo, and another hardware to manage the fifo pointers for the big fifo.

Invention description: On the case of multiple small fifos, the hardware is exactly the same as the one used for the usual method ie consist of read/write counters with some logic to manage the clock domain change, and the empty/full flags.

On the case of one big fifo, the hardware for the fifo is the same as before. The only thing that is changing, is that the received data are written every time in a different fifo.Thus the data are read in a different fifo as well.

For instance when receivi...