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A hybrid substrate injection protection scheme for power ICs

IP.com Disclosure Number: IPCOM000033057D
Original Publication Date: 2004-Nov-23
Included in the Prior Art Database: 2004-Nov-23
Document File: 5 page(s) / 204K

Publishing Venue

Motorola

Related People

Vishnu Khemka: AUTHOR [+4]

Abstract

In this disclosure we propose a novel and unique design for achieving very high levels of protection against injection of minority carriers into the substrate on a power integrated circuits technology. The proposed technique is capable of realizing excellent trade-off between high-side breakdown voltage and substrate injection protection.

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A hybrid substrate injection protection scheme for power ICs

 

Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu and Amitava Bose

Abstract:          In this disclosure we propose a novel and unique design for achieving very high levels of protection against injection of minority carriers into the substrate on a power integrated circuits technology. The proposed technique is capable of realizing excellent trade-off between high-side breakdown voltage and substrate injection protection.

Different types of semiconductor components are often used in automotive and other high voltage applications.  These different types of semiconductor components include discrete devices and integrated circuits.  As an example, the discrete devices can be power Metal-Oxide-Semiconductor (MOS) transistors having source, gate, and drain terminals.  These different types of semiconductor components have been combined onto a single semiconductor chip to reduce the cost and space required for the semiconductor components. 

One significant problem of these combined semiconductor components occurs when the drain terminal of the power MOS transistor is reverse biased.  The reverse biasing of the drain terminal injects minority carriers into the semiconductor substrate, and the minority carriers degrade the performance of the integrated circuit located on the same semiconductor chip.

Several prior attempts have been made to either contain the injected minority carriers or suppress the injection of minority carriers.  These prior attempts, however, still have disadvantages of low drain-to-source breakdown voltage, large epitaxial semiconductor layer thickness, and/or non-isolated power transistors.

Accordingly, a need exists for a semiconductor component with a power transistor combined with an integrated circuit onto a single semiconductor chip where the power transistor has a high drain-to-source breakdown voltage and is isolated from the integrated circuit.  A need also exists for the epitaxial semiconductor layer, in which the power device and the integrated circuit are formed, to have a small thickness.  A further need exists for a method of operating a semiconductor component to suppress the injection of minority carriers into the semiconductor substrate.

A P++ substrate is very effective by itself in suppressing minority carrier (electron) injection by virtue of low carrier lifetime. However, a lightly doped P-epi, which is required above the P++ substrate for high-side breakdown voltage capability significantly, diminishes the electron extinguishing property of the P++ sub. One possibility in a non-trench process is a N+ guard ring that can be grounded or biased to a low su...