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Extension of a Standard Processor to Improve Bit-field Manipulation Capabilities

IP.com Disclosure Number: IPCOM000033081D
Published in the IP.com Journal: Volume 4 Issue 12 (2004-12-25)
Included in the Prior Art Database: 2004-Dec-25
Document File: 4 page(s) / 553K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Generally, communication/networking protocols need to extract, analyze and modify bit-fields. Bit-fields are neighboring multi-bit information within a 16 or 32 bit word, usually carrying specific parameters, such as types, indicators, lengths or addresses. The size of bit-fields can range from one bit to several bytes. Standard processors are capable of handling data of fixed size e.g. 64 bits, some with scalable options of 8/16/32/... They are by nature very cumbersome with sizes like 2, 4, 12, ... which are the common bit-field sizes. For example: If a 32-bit processor wants to modify 12 bits of a 32 bit data it must perform memory read, multiple shifting, several masking operations (in the form of OR/AND) and then writes the modified 32-bit data back to the memory. These operations take several cycles and that degrades the system performance. In addition, these instructions occupy memory space, which is precious in SoCs (Systems on a Chip). Up to now, there are two solutions - pure hardware protocol processing engines and proprietary/in-house processors. In the first solution, the protocol is first analyzed and then the architecture is derived. When implemented in hardware, there will be heavy restrictions on bit-wise access or they might not even exist. The second proposal is to build a proprietary processor that will support bit-field oriented instructions. This may include bit-field extraction, masking, repositioning, bit-wise accesses to external memories and so on. Both solutions have some disadvantages and restrictions, and consume additional cost and time to develop.

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Extension of a Standard Processor to Improve Bit-field Manipulation Capabilities

Idea: Taro Kamiko, SG-Singapore; Juraj Povazanec, SG-Singapore; Biju Sukumaran, SG-

Singapore; Chun Feng Hu, SG-Singapore

Generally, communication/networking protocols need to extract, analyze and modify bit-fields. Bit- fields are neighboring multi-bit information within a 16 or 32 bit word, usually carrying specific parameters, such as types, indicators, lengths or addresses. The size of bit-fields can range from one bit to several bytes. Standard processors are capable of handling data of fixed size e.g. 64 bits, some with scalable options of 8/16/32/... They are by nature very cumbersome with sizes like 2, 4, 12, ... which are the common bit-field sizes.

For example: If a 32-bit processor wants to modify 12 bits of a 32 bit data it must perform memory read, multiple shifting, several masking operations (in the form of OR/AND) and then writes the modified 32-bit data back to the memory. These operations take several cycles and that degrades the system performance. In addition, these instructions occupy memory space, which is precious in SoCs (Systems on a Chip).

Up to now, there are two solutions - pure hardware protocol processing engines and proprietary/in- house processors. In the first solution, the protocol is first analyzed and then the architecture is derived. When implemented in hardware, there will be heavy restrictions on bit-wise access or they might not even exist. The second proposal is to build a proprietary processor that will support bit-field oriented instructions. This may include bit-field extraction, masking, repositioning, bit-wise accesses to external memories and so on. Both solutions have some disadvantages and restrictions, and consume additional cost and time to develop.

The new idea utilizes unused memory space (unused address bus lines) to provide an instruction to the memory controller (reformatting engine). This instruction carries two parameters, the beginning bit position of the accessed bit-field and the bit size of the bit-field. With this information, the reformatting engine can select the specified data bit-lines, either for reading or writing.

With the new idea an attachment is created to an existing general-purpose processor, that will allow it to read or write data from an external memory in a bit-field format, limited to the maximal size of the data bus. Hardware modification of an existing processor's internals is not required. The idea relies in fact that most embedded processors are capable of addressing a huge address space, but very often the memory implemented on the SoC takes up only a small portion of it.

The idea "extends" unused locations by giving access to existing memory via a reformatting engine (memory controller). The parameters for reformatting engine's function are provided directly in unused address bits. Most likely candidate will be the upper most bits of the address bus (or MSB - Most ...