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Browse Prior Art Database

Cost Effective Stacking and Electrical Interconnection of IC Chips

IP.com Disclosure Number: IPCOM000033115D
Original Publication Date: 2004-Dec-25
Included in the Prior Art Database: 2004-Dec-25
Document File: 5 page(s) / 66K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Three-dimensional integration is a rapidly emerging technology that promises to provide substantial benefits in IC functionality and cost in a smaller, more efficient package. A wide variety of heterogeneous technologies can be integrated with this technique, including logic, memory, analog circuits, and sensor/detector technologies. Up to now, neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually "known good" die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. Then, the same-size neo-chips can be efficiently stacked using well-developed processing steps.

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Cost Effective Stacking and Electrical Interconnection of IC Chips

Idea: Harald Gross, DE-Dresden

Three-dimensional integration is a rapidly emerging technology that promises to provide substantial benefits in IC functionality and cost in a smaller, more efficient package. A wide variety of heterogeneous technologies can be integrated with this technique, including logic, memory, analog circuits, and sensor/detector technologies.

Up to now, neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually "known good" die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. Then, the same-size neo-chips can be efficiently stacked using well-developed processing steps.

A method is proposed, which allows a simple and cost effective electrical interconnection of thinned chips of integrated circuits within a stack and packaging thereof. This method has the distinction, that the essential process steps are performed at front-end wafer level, partially on top of the kerf between chips. Thus, the silicon wafer itself acts as carrier and has therefore the same thermal expansion coefficient as each chip.

The benefits of the proposed method are:

* Lithography process steps are replaced by dicing steps, which are less expensive in mass production.

* All fabrication steps, including assembly of dies into a stack are batch processed and thus cost effective.

* The method provides the shortest possible electrical connection around a chip to an interface.

An embodiment of the proposed method is described in the following.

© SIEMENS AG 2004 file: ifx_2004J53744.doc page: 1

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I. Process Flow (1+2 masks)

2. Screen Printing of low outgassing epoxy resin

3. Deposit Seed Layer

4. Lithography I for Metal Traces

50µm + Xµm...